I have extra unopened Cyclone V GX Starter Kit and willing to trade. please send me email if interested. Part Number: P0150 from Terasic Technologies Inc. I am in NC. within US location only.
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Cyclone V GX Starter Kit
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NAND flash booting problem
We made a custom board by using Cyclone5 SE device,as a booting option, provision is given for NAND flash only and there is no other boot option on the board.
we are able to load the the preloader image file successfully into the NAND flash,but when iam observing messages on the Hyper terminal only one message is displaying i.e
U-Boot SPL 2012.10 (Nov 04 2013 - 19:29:22)
There is no other messages are displaying,as per my expectations some of other messages has to be displayed on the terminal like clock configuration history and DDR calibration success.....etc.
The same preloader code,when iam debugging through the JTAG it is working fine and all the above mentioned messages are coming on the hyperterminal.
Please guide me where iam doing the mistake or is there any basic procedural mistake for the NAND flash booting.
Regards
Ravindar-Sigma
we are able to load the the preloader image file successfully into the NAND flash,but when iam observing messages on the Hyper terminal only one message is displaying i.e
U-Boot SPL 2012.10 (Nov 04 2013 - 19:29:22)
There is no other messages are displaying,as per my expectations some of other messages has to be displayed on the terminal like clock configuration history and DDR calibration success.....etc.
The same preloader code,when iam debugging through the JTAG it is working fine and all the above mentioned messages are coming on the hyperterminal.
Please guide me where iam doing the mistake or is there any basic procedural mistake for the NAND flash booting.
Regards
Ravindar-Sigma
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↧
Info: Pin qB han GND driving its datain port
Hello!
I am new in Altera and this is my first program.
Our task is to program the structural diagram (copying the logic diagram) of 74192 IC -- that is, SYNCHRONOUS 4-BIT UP DOWN COUNTER.
We also need to show the waveform diagram of the program and should look like what is in the datasheet.
My problem is it does not do what it should suppose to do and i've checked it many times.
I think, Info: "Pin qB has GND driving its datain port" and "upA is an undefined clock" causes the error (from the warning).
This is my code. Please help me guys :(
My reference datasheet: http://physics.gac.edu/~huber/classe...eets/74192.pdf
module srFlipFlop(q,q1,r,s,clk);//(q,r,s,clk,reset)
output q,q1;
input r,s,clk;
reg q,q1;
initial
begin
q=1'b0;
q1=1'b1;
end
always @(posedge clk )
begin
case({s,r})
{1'b0,1'b0}: begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}: begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=1'bx; q=1'bx; end
endcase
end
endmodule
module PrelimProjectStructural(a, b, c, d, downA, upA, clr, load, bo, co, qA, qB, qC, qD);
input a, b, c, d, downA, upA, clr, load;
output bo, co, qA, qB, qC, qD;
wire notUp, notDown, notClr, notLoad;
wire wSA, wRA, wTA, wQA, wQ1A, wSB, wRB, wTB, wQB, wQ1B, wSC, wRC, wTC, wQC, wQ1C, wSD, wRD, wTD, wQD, wQ1D; //rsff
wire wAndDA, wAndDB, wAndDC, wNandDA, wNandDB, wOrDA, wOrDB;
wire wAndCA, wAndCB, wNandCA, wNandCB, wNandCC, wOrCA, wOrCB;
wire wAndBA, wAndBB, wNandBA, wNandBB, wOrBA, wOrBB;
wire wNandCo, wNandBo;
//nots
not(notUp, upA);
not(notDown, downA);
not(notClr, clr);
not(notLoad, load);
// q'
//not(wQ1A, wQA);
//not(wQ1B, wQB);
//not(wQ1C, wQC);
//not(wQ1D, wQD);
//Part D
and(wAndDA, notUp, wQC, wQB, wQA);
and(wAndDB, notUp, wQD, wQA);
and(wAndDC, wQ1C, wQ1B, wQ1A, notDown);
nand(wNandDA, notClr, notLoad, d);
nand(wNandDB, notLoad, wNandDA);
or(wOrDA, wAndDA, wAndDB, wAndDC);
or(wOrDB, ~notClr, ~wNandDB);
//Part C
and(wAndCA, notUp, wQB, wQA);
and(wAndCB, wQ1B, wQ1A, notDown, wNandCB);//
nand(wNandCA, notClr, notLoad, c);
nand(wNandCB, wQ1D, wQ1C, wQ1B);
nand(wNandCC, notLoad, wNandCA);
or(wOrCA, wAndCA, wAndCB);
or(wOrCB, ~notClr, wNandCC);
//Part B
and(wAndBA, notUp, wQ1D, wQA);
and(wAndBB, wNandCB, wQ1A, notDown);
nand(wNandBA, notClr, notLoad, b);
nand(wNandBB, notLoad, wNandBA);
or(wOrBA, wAndBA, wAndBB);
or(wOrBB, ~notClr, wNandBB);
//Part A
wire wNandAA, wNandAB, wOrAA, wOrAB;
nand(wNandAA, notClr, notLoad, a);
nand(wNandAB, notLoad,wNandAA);
or(wOrAA, notUp, notDown);
or(wOrAB, ~notClr, ~wNandAB);
//others
nand(wNandCo, notUp, wQD, wQA);
nand(wNandBo, wQ1D, wQ1C, wQ1B, wQ1A, notDown);
//flip flops
// q,q1,r,s,clk
srFlipFlop srD(.q(wQD), .q1(wQ1D), .r(wOrDB), .s(~wNandDA), .clk(~wOrDA));
srFlipFlop srC(.q(wQC), .q1(wQ1C), .r(wOrCB), .s(~wNandCA), .clk(~wOrCA));
srFlipFlop srB(.q(wQB), .q1(wQ1B), .r(wOrBB), .s(~wNandBA), .clk(~wOrBA));
srFlipFlop srA(.q(wQA), .q1(wQ1A), .r(wOrAB), .s(~wNandAA), .clk(~wOrAA));
// output bo, co, qA, qB, qC, qD;
assign bo = wNandBo;
assign co = wNandCo;
assign qA = wQA;
assign qB = wQB;
assign qC = wQC;
assign qD = wQD;
endmodule
I am new in Altera and this is my first program.
Our task is to program the structural diagram (copying the logic diagram) of 74192 IC -- that is, SYNCHRONOUS 4-BIT UP DOWN COUNTER.
We also need to show the waveform diagram of the program and should look like what is in the datasheet.
My problem is it does not do what it should suppose to do and i've checked it many times.
I think, Info: "Pin qB has GND driving its datain port" and "upA is an undefined clock" causes the error (from the warning).
This is my code. Please help me guys :(
My reference datasheet: http://physics.gac.edu/~huber/classe...eets/74192.pdf
module srFlipFlop(q,q1,r,s,clk);//(q,r,s,clk,reset)
output q,q1;
input r,s,clk;
reg q,q1;
initial
begin
q=1'b0;
q1=1'b1;
end
always @(posedge clk )
begin
case({s,r})
{1'b0,1'b0}: begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}: begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=1'bx; q=1'bx; end
endcase
end
endmodule
module PrelimProjectStructural(a, b, c, d, downA, upA, clr, load, bo, co, qA, qB, qC, qD);
input a, b, c, d, downA, upA, clr, load;
output bo, co, qA, qB, qC, qD;
wire notUp, notDown, notClr, notLoad;
wire wSA, wRA, wTA, wQA, wQ1A, wSB, wRB, wTB, wQB, wQ1B, wSC, wRC, wTC, wQC, wQ1C, wSD, wRD, wTD, wQD, wQ1D; //rsff
wire wAndDA, wAndDB, wAndDC, wNandDA, wNandDB, wOrDA, wOrDB;
wire wAndCA, wAndCB, wNandCA, wNandCB, wNandCC, wOrCA, wOrCB;
wire wAndBA, wAndBB, wNandBA, wNandBB, wOrBA, wOrBB;
wire wNandCo, wNandBo;
//nots
not(notUp, upA);
not(notDown, downA);
not(notClr, clr);
not(notLoad, load);
// q'
//not(wQ1A, wQA);
//not(wQ1B, wQB);
//not(wQ1C, wQC);
//not(wQ1D, wQD);
//Part D
and(wAndDA, notUp, wQC, wQB, wQA);
and(wAndDB, notUp, wQD, wQA);
and(wAndDC, wQ1C, wQ1B, wQ1A, notDown);
nand(wNandDA, notClr, notLoad, d);
nand(wNandDB, notLoad, wNandDA);
or(wOrDA, wAndDA, wAndDB, wAndDC);
or(wOrDB, ~notClr, ~wNandDB);
//Part C
and(wAndCA, notUp, wQB, wQA);
and(wAndCB, wQ1B, wQ1A, notDown, wNandCB);//
nand(wNandCA, notClr, notLoad, c);
nand(wNandCB, wQ1D, wQ1C, wQ1B);
nand(wNandCC, notLoad, wNandCA);
or(wOrCA, wAndCA, wAndCB);
or(wOrCB, ~notClr, wNandCC);
//Part B
and(wAndBA, notUp, wQ1D, wQA);
and(wAndBB, wNandCB, wQ1A, notDown);
nand(wNandBA, notClr, notLoad, b);
nand(wNandBB, notLoad, wNandBA);
or(wOrBA, wAndBA, wAndBB);
or(wOrBB, ~notClr, wNandBB);
//Part A
wire wNandAA, wNandAB, wOrAA, wOrAB;
nand(wNandAA, notClr, notLoad, a);
nand(wNandAB, notLoad,wNandAA);
or(wOrAA, notUp, notDown);
or(wOrAB, ~notClr, ~wNandAB);
//others
nand(wNandCo, notUp, wQD, wQA);
nand(wNandBo, wQ1D, wQ1C, wQ1B, wQ1A, notDown);
//flip flops
// q,q1,r,s,clk
srFlipFlop srD(.q(wQD), .q1(wQ1D), .r(wOrDB), .s(~wNandDA), .clk(~wOrDA));
srFlipFlop srC(.q(wQC), .q1(wQ1C), .r(wOrCB), .s(~wNandCA), .clk(~wOrCA));
srFlipFlop srB(.q(wQB), .q1(wQ1B), .r(wOrBB), .s(~wNandBA), .clk(~wOrBA));
srFlipFlop srA(.q(wQA), .q1(wQ1A), .r(wOrAB), .s(~wNandAA), .clk(~wOrAA));
// output bo, co, qA, qB, qC, qD;
assign bo = wNandBo;
assign co = wNandCo;
assign qA = wQA;
assign qB = wQB;
assign qC = wQC;
assign qD = wQD;
endmodule
↧
URGENT URGENT URGENT! 74192 behavioral circuit
Hello guys, Im new in this website. Do you have a circuit that behaves like of 74192 SYNCHRONOUS 4-BIT UP/DOWN COUNTER
this is the datasheet
http://physics.gac.edu/~huber/classe...eets/74192.pdf
this is the datasheet
http://physics.gac.edu/~huber/classe...eets/74192.pdf
↧
EP1K100 failure issue
EP1K100, PQFP package i am using for an old design, which is failing for 2.5V core supply with oscillator. Anyone had any observation of core volatge 2.5 V faliure or short to ground?
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↧
Upgradng QSYS VIP to Quartus 14
I have been developing with the VIP suite using Quartus 13.1 for some months, all working happily. I have upgraded to Quartus 14, and all worked fine until I regenerated the QSYS part of the project.
After regenerating, the Clocked Video Output no longer locks to my SOF pulse, and reports underflow, however there is no evidence of underflow on the output picture. The timing with respect to my reference comes up randomly as it no longer locks to SOF.
The QSYS VIP blocks I am using are a Frame Reader -> Interlacer -> Clocked Video Output. There is more than enough bandwidth as there is a dedicated DDR3 bank for this video playout, and no other access going on.
The problem persists whether I have the interlacer in bypass or not, and in all video standards I try, all of which worked fine in Quartus 13.1.
I have also tried Quartus 14.1, and tried migrating to Clocked Video Output II with similar results. I have now rolled back to Quartus 13.1, but would like to move to the latest revision of Quartus.
Has anyone else had similar trouble with upgrading to Quartus 14?
After regenerating, the Clocked Video Output no longer locks to my SOF pulse, and reports underflow, however there is no evidence of underflow on the output picture. The timing with respect to my reference comes up randomly as it no longer locks to SOF.
The QSYS VIP blocks I am using are a Frame Reader -> Interlacer -> Clocked Video Output. There is more than enough bandwidth as there is a dedicated DDR3 bank for this video playout, and no other access going on.
The problem persists whether I have the interlacer in bypass or not, and in all video standards I try, all of which worked fine in Quartus 13.1.
I have also tried Quartus 14.1, and tried migrating to Clocked Video Output II with similar results. I have now rolled back to Quartus 13.1, but would like to move to the latest revision of Quartus.
Has anyone else had similar trouble with upgrading to Quartus 14?
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USB-Blaster: Unable to read device chain - JTAG chain broken
I'm using Ubuntu14.04 and quartus14.1. When I run jtagconfig, I get:
$ jtagconfig
1) USB-Blaster [3-6]
Unable to read device chain - JTAG chain broken
The hardware is correct because I can read the JTAG chain using a old PC.
Some extra information:
$ cat /etc/udev/rules.d/51-usbblaster.rules# USB-Blaster
## from http://www.fpga-dev.com/altera-usb-blaster-with-ubuntu/
# For Altera USB-Blaster permissions.
SUBSYSTEM=="usb",\
ENV{DEVTYPE}=="usb_device",\
ATTR{idVendor}=="09fb",\
ATTR{idProduct}=="6001",\
MODE="0666",\
NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\
RUN+="/bin/chmod 0666 %c"
$ ls -l /etc/jtagd/pgm_parts.txt
-rw-r--r-- 1 root root 921110 Jan 12 12:54 /etc/jtagd/pgm_parts.txt
I have also re-run:
$ sudo udevadm control --reload
But nothing help!
Any tips?
$ jtagconfig
1) USB-Blaster [3-6]
Unable to read device chain - JTAG chain broken
The hardware is correct because I can read the JTAG chain using a old PC.
Some extra information:
$ cat /etc/udev/rules.d/51-usbblaster.rules# USB-Blaster
## from http://www.fpga-dev.com/altera-usb-blaster-with-ubuntu/
# For Altera USB-Blaster permissions.
SUBSYSTEM=="usb",\
ENV{DEVTYPE}=="usb_device",\
ATTR{idVendor}=="09fb",\
ATTR{idProduct}=="6001",\
MODE="0666",\
NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\
RUN+="/bin/chmod 0666 %c"
$ ls -l /etc/jtagd/pgm_parts.txt
-rw-r--r-- 1 root root 921110 Jan 12 12:54 /etc/jtagd/pgm_parts.txt
I have also re-run:
$ sudo udevadm control --reload
But nothing help!
Any tips?
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tse_sgmii_lvds_altera_lvds_core20_141_..sdc: -1 could not be matched with with a port
Hello,
In our Arria10 FPGA design we are implementing the Triple-Speed-Ethernet ip block. This ip block needs a REFCLK of 125MHz.
Ideally I want to connect this refclk to a PLL output. This PLL is an Altera IOPLL.
After generating and connecting the Altera IOPLL and the TSE ip blocks (using the IP catalog in Quartus v14.1), I'm facing problems in TimeQuest, hold- and setup timing issues related to this REFCLK.
After studying the compilation report, I found out that the REFCLK (is output of my PLL) is not found:
Warning (332174): Ignored filter at ip_arria10_tse_sgmii_lvds_altera_lvds_core20_141_v xotqby.sdc(123): -1 could not be matched with a port
This line 123 in the sdc file: set ref_ck_pin [get_port_info -name $ref_ck_port_id]
Interesting to know when I'm not using the PLL (connect REFCLK to a real FPGA pin), there are no timing issues.
Do you have a suggestion how to make it working with the PLL? How to make the Fitter find the right clock so that the warning goes away?
thanks,
Leon
In our Arria10 FPGA design we are implementing the Triple-Speed-Ethernet ip block. This ip block needs a REFCLK of 125MHz.
Ideally I want to connect this refclk to a PLL output. This PLL is an Altera IOPLL.
After generating and connecting the Altera IOPLL and the TSE ip blocks (using the IP catalog in Quartus v14.1), I'm facing problems in TimeQuest, hold- and setup timing issues related to this REFCLK.
After studying the compilation report, I found out that the REFCLK (is output of my PLL) is not found:
Warning (332174): Ignored filter at ip_arria10_tse_sgmii_lvds_altera_lvds_core20_141_v xotqby.sdc(123): -1 could not be matched with a port
This line 123 in the sdc file: set ref_ck_pin [get_port_info -name $ref_ck_port_id]
Interesting to know when I'm not using the PLL (connect REFCLK to a real FPGA pin), there are no timing issues.
Do you have a suggestion how to make it working with the PLL? How to make the Fitter find the right clock so that the warning goes away?
thanks,
Leon
↧
SPI from HPS through FPGA not working
Hello,
Since 6 month i am working with SOC Cyclone V Evalboard from Altera.
I use Yocto to build linux and EDS V 14.0 for development.
For Knowledge and HowTo my first place is Rocketboards, but i also use Searchengines to find answers ;)
With the Evalboard i use I2C, SPI and GPIOs(all from HPS) as interface to other devices like display, port expander, leds, gpios,... without problems.
Now i want to route the spi pins from the hps to the fpga.
After this, if i want to send something over the spi, i get a cpu stall and nothing works anymore. Need to reset the board.
Is it not so simple to route the hps pins to the fpga? with the loanpins i also had no problems.
I hope anybody can give me a hint.
Best regards
Alex
Since 6 month i am working with SOC Cyclone V Evalboard from Altera.
I use Yocto to build linux and EDS V 14.0 for development.
For Knowledge and HowTo my first place is Rocketboards, but i also use Searchengines to find answers ;)
With the Evalboard i use I2C, SPI and GPIOs(all from HPS) as interface to other devices like display, port expander, leds, gpios,... without problems.
Now i want to route the spi pins from the hps to the fpga.
- 'exported' the pins in qsys.
- routed the exported pins to the leds in quartus
- Create all needed files. preloader, u-boot, dtb
After this, if i want to send something over the spi, i get a cpu stall and nothing works anymore. Need to reset the board.
Is it not so simple to route the hps pins to the fpga? with the loanpins i also had no problems.
I hope anybody can give me a hint.
Best regards
Alex
↧
↧
latest kernel release
what is the latest kernel version that supported by altera?
↧
Using multiple BFMs in VHDL / Problems with use clauses
Hi.
I'm trying to create a VHDL testbench using Altera Verification BFMs.
The DUT has an Avalon-MM Slave Interface, an Avalon-ST Sink Interface and an Avalon-ST Source Interface. The generated QSYS system has an Avalon-MM Master BFM, an Avalon-ST Source BFM and an Avalon-ST Sink interface.
I can't make it work when I use more than one interface.
Consider this [simplified] example:
This works fine and I'm able to see the Source BFM sending data to my module Sink Interface in ModelSim waveform window.
However, I can't make it work when I try another interface.
If I ->
1) Don't insert any library / use clause in the VHDL file: ModelSim complains it can't find the functions. [That's expected]. This happens even if I write them in the form library.package.function_name.
2) Insert both libraries + use clauses at the beginning of the VHDL file: ModelSim doesn't know from which library it should use the functions.
[That's also expected].
However if I use the full name, as in library.package.function, I still get an error:
[This should work, if I'm not mistaken].
3) Insert both libraries at the top of the file, and the use clauses in separate process (that's what the example test_program_pkg.vhd provided by Altera also does):
I get the same error as in (2).
Could anybody explain to me what I'm doing wrong? What's the proper way to instantiate the provided BFMs functions in VHDL testbenches?
I'm trying to create a VHDL testbench using Altera Verification BFMs.
The DUT has an Avalon-MM Slave Interface, an Avalon-ST Sink Interface and an Avalon-ST Source Interface. The generated QSYS system has an Avalon-MM Master BFM, an Avalon-ST Source BFM and an Avalon-ST Sink interface.
I can't make it work when I use more than one interface.
Consider this [simplified] example:
Code:
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library bfm_test_mymodulesink_bfm;
use bfm_test_mymodulesink_bfm.altera_avalon_st_source_bfm_vhdl_pkg.all;
<entity declaration>
<architecture declaration>
process is
begin
set_transaction_channel(channel, id, req_if(id));
set_transaction_data(data, id, req_if(id));
push_transaction(id, req_if(id));
end process;However, I can't make it work when I try another interface.
If I ->
1) Don't insert any library / use clause in the VHDL file: ModelSim complains it can't find the functions. [That's expected]. This happens even if I write them in the form library.package.function_name.
2) Insert both libraries + use clauses at the beginning of the VHDL file: ModelSim doesn't know from which library it should use the functions.
Code:
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library bfm_test_mymodulesink_bfm;
use bfm_test_mymodulesink_bfm.altera_avalon_st_source_bfm_vhdl_pkg.all;
library bfm_test_mymodulesource_bfm;
use bfm_test_mymodulesource_bfm.altera_avalon_st_sink_bfm_vhdl_pkg.all;
library bfm_test_mymoduleavmm_bfm;
use bfm_test_mymoduleavmm_bfm.altera_avalon_mm_master_bfm_vhdl_pkg.all;
<entity declaration>
<architecture declaration>
process is
begin
set_transaction_channel(channel, id, req_if(id));
set_transaction_data(data, id, req_if(id));
push_transaction(id, req_if(id));
end process;Code:
# ** Error: ./../teste_bfm_sys_tb.vhd(568): (vcom-1078) Identifier "req_if" is not directly visible.However if I use the full name, as in library.package.function, I still get an error:
Code:
bfm_test_mymodulesink_bfm.altera_avalon_st_source_bfm_vhdl_pkg.req_if(0)Code:
# ** Error: ./../teste_bfm_sys_tb.vhd(568): Illegal expanded name prefix ("bfm_test_mymodulesink_bfm" is not label of block, process, generate, or (for) loop statement).
# ** Error: ./../teste_bfm_sys_tb.vhd(568): (vcom-1195) Cannot find expanded name "bfm_test_mymodulesink_bfm.altera_avalon_st_source_bfm_vhdl_pkg".3) Insert both libraries at the top of the file, and the use clauses in separate process (that's what the example test_program_pkg.vhd provided by Altera also does):
Code:
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library bfm_test_mymodulesink_bfm;
--use bfm_test_mymodulesink_bfm.altera_avalon_st_source_bfm_vhdl_pkg.all;
library bfm_test_mymodulesource_bfm;
--use bfm_test_mymodulesource_bfm.altera_avalon_st_sink_bfm_vhdl_pkg.all;
library bfm_test_mymoduleavmm_bfm;
--use bfm_test_mymoduleavmm_bfm.altera_avalon_mm_master_bfm_vhdl_pkg.all;
<entity declaration>
<architecture declaration>
source_bfm_process : process is
use bfm_test_mymodulesink_bfm.altera_avalon_st_source_bfm_vhdl_pkg.all;
begin
set_transaction_channel(channel, id, req_if(id));
set_transaction_data(data, id, req_if(id));
push_transaction(id, req_if(id));
end process source_bfm;
<processes for sink / master>Code:
"Illegal expanded name prefix"
"Cannot find expanded name" / "Unknown expanded name".↧
IO discrepancy between CIC 10.1 and 13.1
I'm upgrading IP and I see an IO mismatch between the output data widths of the CIC core generated in 10.1 versus the one from 13.1. The documentation for both shows the same formula for calculating output width:
Bin + Nlog2(RM) - log2(R)
For me, this comes out to 45.68. The 10.1 design generates 47 bits and the 13.1 design generates 46 bits. Although the 13.1 design seems more accurate, I've already verified the design with the 10.1 core. I've generated other cores and have noticed that the 10.1 compiler consistently adds 1 bit to the output. Can anyone tell me if I need to drop a bit or shift a bit to match the previous behavior? Or did the algorithm get updated, and I can no longer expect a bit accurate match to my previous design?
Alex
Bin + Nlog2(RM) - log2(R)
For me, this comes out to 45.68. The 10.1 design generates 47 bits and the 13.1 design generates 46 bits. Although the 13.1 design seems more accurate, I've already verified the design with the 10.1 core. I've generated other cores and have noticed that the 10.1 compiler consistently adds 1 bit to the output. Can anyone tell me if I need to drop a bit or shift a bit to match the previous behavior? Or did the algorithm get updated, and I can no longer expect a bit accurate match to my previous design?
Alex
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help!..FPGA based led lighting where d lights come on at night and goes off at day
Good day guys!...I'm totally new to hardware implementation using FPGA but I can do this using microcontrollers.I have d altera de2 board and i have been having a hard time learning d vhdl code to implement this...pls help this newbie out,it will go a long way in encouraging me if I can implement it on the de2 board
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help! .FPGA based led lighting where d lights come on at night and goes off at day
Good day guys!...I'm totally new to hardware implementation using FPGA but I can do this using microcontrollers.I have d altera de2 board and i have been having a hard time learning d vhdl code to implement this...pls help this newbie out,it will go a long way in encouraging me if I can implement it on the de2 board.
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USB Blaster JTAG chain broken
I'm using Ubuntu14.04 and quartus14.1. When I run jtagconfig, I get
:
$ jtagconfig
1) USB-Blaster [3-6]
Unable to read device chain - JTAG chain broken
The hardware is correct because I can read the JTAG chain using a old PC.
Some extra information:
$ cat /etc/udev/rules.d/51-usbblaster.rules# USB-Blaster
## from http://www.fpga-dev.com/altera-usb-blaster-with-ubuntu/
# For Altera USB-Blaster permissions.
SUBSYSTEM=="usb",\
ENV{DEVTYPE}=="usb_device",\
ATTR{idVendor}=="09fb",\
ATTR{idProduct}=="6001",\
MODE="0666",\
NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\
RUN+="/bin/chmod 0666 %c"
$ ls -l /etc/jtagd/pgm_parts.txt
-rw-r--r-- 1 root root 921110 Jan 12 12:54 /etc/jtagd/pgm_parts.txt
I have also re-run:
$ sudo udevadm control --reload
But nothing help!
Any tips?
:
$ jtagconfig
1) USB-Blaster [3-6]
Unable to read device chain - JTAG chain broken
The hardware is correct because I can read the JTAG chain using a old PC.
Some extra information:
$ cat /etc/udev/rules.d/51-usbblaster.rules# USB-Blaster
## from http://www.fpga-dev.com/altera-usb-blaster-with-ubuntu/
# For Altera USB-Blaster permissions.
SUBSYSTEM=="usb",\
ENV{DEVTYPE}=="usb_device",\
ATTR{idVendor}=="09fb",\
ATTR{idProduct}=="6001",\
MODE="0666",\
NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\
RUN+="/bin/chmod 0666 %c"
$ ls -l /etc/jtagd/pgm_parts.txt
-rw-r--r-- 1 root root 921110 Jan 12 12:54 /etc/jtagd/pgm_parts.txt
I have also re-run:
$ sudo udevadm control --reload
But nothing help!
Any tips?
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what happened about "ip-generate FAILED" ?
when I aoced hello_world, it emerged some errors,
"Code path doesn't support quarter-rate yet"
"Error: system.board.pcie: Selected device family :Cyclone V is not supported"
...
now, I compile hello_world without FPGA board.
Thanks!
"Code path doesn't support quarter-rate yet"
"Error: system.board.pcie: Selected device family :Cyclone V is not supported"
...
now, I compile hello_world without FPGA board.
Thanks!
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NiosII, No ELF file path has been selected
Hello everyone ,
I written a PID controller in NiosII, hello_world_small,yesterday, and everyting was OK.
I change some codes just now, and I get message :
Errors(3 items)
address 0xbfdc of PID1.elf section,'bss' is not withinregion'onchip_memory'
address 0xbdfc of PID1.elf section ,'onchip_memory' is not within region'onchip_memory'
make:***[PID1.elf]Error 1
And I check the Run configurations,the message is :
No ELF file path has been selected.
What's going on?:( How to generate the ELF file?:confused:
I written a PID controller in NiosII, hello_world_small,yesterday, and everyting was OK.
I change some codes just now, and I get message :
Errors(3 items)
address 0xbfdc of PID1.elf section,'bss' is not withinregion'onchip_memory'
address 0xbdfc of PID1.elf section ,'onchip_memory' is not within region'onchip_memory'
make:***[PID1.elf]Error 1
And I check the Run configurations,the message is :
No ELF file path has been selected.
What's going on?:( How to generate the ELF file?:confused:
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build issue with EDS
hi all,
I built hello_world through make -f Makefile command, but it showed"arm-linux-gnueabinf-g++: error : /libpath:C:/altera/14.1/hld/host/windows64/lib/: Invalid argument", "arm-linux-gnueabinf-g++: error :alteracl.lib: no such file or directory" ......
It seems the path C:/altera/14.1/hld/host/windows64/lib/ is invalid on windows. this path seems to be modified to /cygdrive/c/altera/14.1/hld/host/windows64/lib/ ? and which file should I modify? or solve it in another way.
Thanks
I built hello_world through make -f Makefile command, but it showed"arm-linux-gnueabinf-g++: error : /libpath:C:/altera/14.1/hld/host/windows64/lib/: Invalid argument", "arm-linux-gnueabinf-g++: error :alteracl.lib: no such file or directory" ......
It seems the path C:/altera/14.1/hld/host/windows64/lib/ is invalid on windows. this path seems to be modified to /cygdrive/c/altera/14.1/hld/host/windows64/lib/ ? and which file should I modify? or solve it in another way.
Thanks
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SGDMA streaming to memory, how to start and stop?
I've read a couple of posts about the SGDMA on this forum, but can't see an answer to the specific problem I'm having.
Our design has a streaming source that runs continuously. We need to capture a chunk of data from this stream into memory.
The stream is running quite fast (64bits of data valid every 4 clock cycles), and uses burst writes to move this into memory via a 64 bit bus.
The problem I've come up against is how do I control the flow data into the SGDMA? Even when the SGDMA isn't busy it looks like the FIFO in the SGDMA is filled up. The first samples in my captured data are clearly from some old data. Also because the system is starting with a full FIFO it can't ever run it down to a point where it doesn't overflow again.
The only solution I can see at the moment is to put some logic in so that the Nios can disable the valid from the source to the SGDMA. The Nios would then setup and start the SGDMA before enabling the valid. This problem here is that I'd still end up with data left in the SGDMA FIFO when the capture to memory is completed, as I wouldn't be able to switch off the valid at the instant the SGDMA is finished. I can't see any way to flush this unwanted data out of the SGDMA.
Is there any way that my streaming source can detect that the SGDMA is busy? The 'ready' signal doesn't give me this information as it is asserted when there is space in the SGDMAs FIFO.
Any ideas would be appreciated.
Our design has a streaming source that runs continuously. We need to capture a chunk of data from this stream into memory.
The stream is running quite fast (64bits of data valid every 4 clock cycles), and uses burst writes to move this into memory via a 64 bit bus.
The problem I've come up against is how do I control the flow data into the SGDMA? Even when the SGDMA isn't busy it looks like the FIFO in the SGDMA is filled up. The first samples in my captured data are clearly from some old data. Also because the system is starting with a full FIFO it can't ever run it down to a point where it doesn't overflow again.
The only solution I can see at the moment is to put some logic in so that the Nios can disable the valid from the source to the SGDMA. The Nios would then setup and start the SGDMA before enabling the valid. This problem here is that I'd still end up with data left in the SGDMA FIFO when the capture to memory is completed, as I wouldn't be able to switch off the valid at the instant the SGDMA is finished. I can't see any way to flush this unwanted data out of the SGDMA.
Is there any way that my streaming source can detect that the SGDMA is busy? The 'ready' signal doesn't give me this information as it is asserted when there is space in the SGDMAs FIFO.
Any ideas would be appreciated.
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DDR3 Controller with UniPhy User Interface Issue for Stratix V
Hi all,
I have been using bitware s5ph-q board which has on-board 2 banks of ddr3 ram, each of 4GB. I need to test the memory so that I can use it for my project.
In DDR3 controller with uniphy parameter window, I set row width to 16, column width to 10, bank width to 3 and interface width to 64 which maps to 4GB according to formula provided in altera knowledge base.
http://www.altera.com/support/kdb/so...02012_132.html
But when I generated my Qsys project, the user interface which is an avalon-mm slave interface had address width of 26 bits and writedata and readdata of 512 bits.
In general we know that, to access 4GB we need 32-bit address. But I can't able to understand how DDR3 controller is managing it by 26 bits.
And also observed that the writedata and readdata are dependent on the interface width parameter, being multiple of 8 (in this case 64*8=512).
So I have a confusion of how to provide data to the controller so that I can have access to complete 4GB.
Is anyone here has a proper explanation?
Thanks in advance :)
I have been using bitware s5ph-q board which has on-board 2 banks of ddr3 ram, each of 4GB. I need to test the memory so that I can use it for my project.
In DDR3 controller with uniphy parameter window, I set row width to 16, column width to 10, bank width to 3 and interface width to 64 which maps to 4GB according to formula provided in altera knowledge base.
http://www.altera.com/support/kdb/so...02012_132.html
But when I generated my Qsys project, the user interface which is an avalon-mm slave interface had address width of 26 bits and writedata and readdata of 512 bits.
In general we know that, to access 4GB we need 32-bit address. But I can't able to understand how DDR3 controller is managing it by 26 bits.
And also observed that the writedata and readdata are dependent on the interface width parameter, being multiple of 8 (in this case 64*8=512).
So I have a confusion of how to provide data to the controller so that I can have access to complete 4GB.
Is anyone here has a proper explanation?
Thanks in advance :)
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