Hi,
Does anyone know if Signal Tap can be used with .pof? If yes is there any guide? Thanks!
Regards,
Vinhael
Does anyone know if Signal Tap can be used with .pof? If yes is there any guide? Thanks!
Regards,
Vinhael
↧
Using Signal Tap with .pof
↧
DE1-SoC HPS DDR3 Controller with UniPHY fitter error
Hello,
I'm trying to access the HPS DDR3 directly from the FPGA on the DE1-SoC board but I have some fitter issues. In order to access the memory I used SoCKit vip demo as the reference as the DDR3 memory is used there. In the DE1-SoC vip demo reference design in QSys I changed the memory from sdram controller to DDR3 SDRAM controller with UniPHY. I mapped the pin locations for the DDR3 memory in the Assignments Editor according to DE1-SoC user manual. I also set I/O Standard as it is in the documentation. I also wired the controller and hps exported conduits in the quartus verilog design just as it is done in the SoCKit demo. The only problem is I get errors during fitting:
These go for all HPS_DDR3 pins in the design. Right now I don't have a clue what may be the cause of this error. I'm using Quartus 15.0, I know the demos were compiled for Quartus 13, but is there a difference that may cause such errors? I also run the .tcl scripts for pin assignments but it didn't help. Any ideas would be much appreciated.
Best regards
I'm trying to access the HPS DDR3 directly from the FPGA on the DE1-SoC board but I have some fitter issues. In order to access the memory I used SoCKit vip demo as the reference as the DDR3 memory is used there. In the DE1-SoC vip demo reference design in QSys I changed the memory from sdram controller to DDR3 SDRAM controller with UniPHY. I mapped the pin locations for the DDR3 memory in the Assignments Editor according to DE1-SoC user manual. I also set I/O Standard as it is in the documentation. I also wired the controller and hps exported conduits in the quartus verilog design just as it is done in the SoCKit demo. The only problem is I get errors during fitting:
Code:
Error (14566): Could not place 31 periphery component(s) due to conflicts with existing constraints (31 pin(s))
Error (175020): Illegal constraint of pin to the region (89, 69) to (89, 80): no valid locations in region
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): HPS_DDR3_RZQ
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (184016): There were not enough single-ended input pin locations available (1 location affected)
Info (175029): D27
Info (175015): The I/O pad HPS_DDR3_RZQ is constrained to the location PIN_D27 due to: User Location Constraints (PIN_D27)
Info (14709): The constrained I/O pad is contained within this pin
Error (175020): Illegal constraint of pin to the region (89, 69) to (89, 80): no valid locations in region
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): HPS_DDR3_ADDR[0]
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (184016): There were not enough single-ended output pin locations available (1 location affected)
Info (175029): F26
Info (175015): The I/O pad HPS_DDR3_ADDR[0] is constrained to the location PIN_F26 due to: User Location Constraints (PIN_F26)
Info (14709): The constrained I/O pad is contained within this pin
These go for all HPS_DDR3 pins in the design. Right now I don't have a clue what may be the cause of this error. I'm using Quartus 15.0, I know the demos were compiled for Quartus 13, but is there a difference that may cause such errors? I also run the .tcl scripts for pin assignments but it didn't help. Any ideas would be much appreciated.
Best regards
↧
↧
NCO compile freeze
Hi
I'm using quartus II 13.0 WEB with a DE1 board at my University.
Im trying to generate a sine with cordic algoritm using Megafunction NCO.
During NCO creation the operation "freeze" at "generating megacore function top-level..."
I tryed different configuration and use multipliers instead cordic, but i had the same problem.
There is something i have to do to unfreeze?
Max
I'm using quartus II 13.0 WEB with a DE1 board at my University.
Im trying to generate a sine with cordic algoritm using Megafunction NCO.
During NCO creation the operation "freeze" at "generating megacore function top-level..."
I tryed different configuration and use multipliers instead cordic, but i had the same problem.
There is something i have to do to unfreeze?
Max
↧
About VGA Output
Hello,
I am working for the first time with FPGA (cyclone v soc) and i am trying to get a output from VGA Port on the monitor. I have set the resolution for 1024x768 and PLL input frequency as 50MHz and output frequency as 65MHz as required for the resolution.But as soon as i program the board the monitor is going to sleep mode. I am attaching the code which i used for this. Can you please tell me what may be the problem. When I checked in RTL Simulation PLL is not generating any clock output.
Thank you in advance.
Code:
----Main code
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY VGA IS
PORT(
CLOCK_24: IN STD_LOGIC;
SYS_rst : IN STD_LOGIC;
VGA_HS, VGA_VS: OUT STD_LOGIC;
VGA_R, VGA_G, VGA_B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_CLK_65MHZ : OUT STD_LOGIC
);
END VGA;
ARCHITECTURE MAIN OF VGA IS
SIGNAL VGACLK, RESET, lock : STD_LOGIC :='0';
signal SIGNAL_135MHZ : STD_LOGIC:= '0';
COMPONENT SYNC IS
PORT
(
CLK : IN STD_LOGIC;
HSYNC, VSYNC : out std_logic;
R, G, B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
component unsaved is -- PLL Component
port (
pll_0_locked_export : out std_logic; -- pll_0_locked.export
pll_0_outclk0_clk : out std_logic; -- clk
pll_0_refclk_clk : in std_logic := '0'; -- clk
pll_0_reset_reset : in std_logic := '0' -- reset
);
end component unsaved;
BEGIN
inst_pll : UNSAVED port map
(
pll_0_refclk_clk => clock_24,
pll_0_reset_reset => SYS_rst,
pll_0_outclk0_clk => VGACLK, ---CLOCK 65 MHZ
--outclk_1 => SIGNAL_135MHZ, --- CLOCK 135 MHZ
pll_0_locked_export => lock
);
INST_SYNC : SYNC PORT MAP
(
CLK => VGACLK,
HSYNC => VGA_HS,
VSYNC => VGA_VS,
R => VGA_R,
G => VGA_G,
B => VGA_B
);
VGA_CLK_65MHZ <= VGACLK;
END MAIN;
---Sub Program
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY SYNC IS
PORT(
CLK : IN STD_LOGIC;
HSYNC, VSYNC : out std_logic;
R, G, B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END SYNC;
ARCHITECTURE MAIN OF SYNC IS
SIGNAL HPOS: INTEGER RANGE 0 TO 800:=0;
SIGNAL VPOS: INTEGER RANGE 0 TO 525:=0;
BEGIN
PROCESS(CLK,HPOS,VPOS)
BEGIN
IF(CLK' EVENT AND CLK='1') THEN
IF (HPOS = 480 OR VPOS = 285) THEN
R <= (OTHERS => '1');
G <= (OTHERS => '1');
B <= (OTHERS => '1');
ELSE
R <= (OTHERS => '0');
G <= (OTHERS => '0');
B <= (OTHERS => '0');
END IF;
IF(HPOS<800) THEN
HPOS <= HPOS+1;
ELSE
HPOS <=0;
END IF;
IF (VPOS<525)THEN
VPOS <= VPOS+1;
ELSE
VPOS <=0;
END IF;
END IF;
IF (HPOS > 16 AND HPOS < 112)THEN
HSYNC <= '0';
ELSE
HSYNC <= '1';
END IF;
IF (VPOS > 0 AND VPOS < 12) THEN
VSYNC <= '0';
ELSE
VSYNC <= '1';
END IF;
IF ((HPOS> 0 AND HPOS< 160) OR (VPOS>0 AND VPOS< 45)) THEN
R <= (OTHERS => '0');
G <= (OTHERS => '0');
B <= (OTHERS => '0');
END IF;
END PROCESS;
END MAIN;
I am working for the first time with FPGA (cyclone v soc) and i am trying to get a output from VGA Port on the monitor. I have set the resolution for 1024x768 and PLL input frequency as 50MHz and output frequency as 65MHz as required for the resolution.But as soon as i program the board the monitor is going to sleep mode. I am attaching the code which i used for this. Can you please tell me what may be the problem. When I checked in RTL Simulation PLL is not generating any clock output.
Thank you in advance.
Code:
----Main code
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY VGA IS
PORT(
CLOCK_24: IN STD_LOGIC;
SYS_rst : IN STD_LOGIC;
VGA_HS, VGA_VS: OUT STD_LOGIC;
VGA_R, VGA_G, VGA_B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_CLK_65MHZ : OUT STD_LOGIC
);
END VGA;
ARCHITECTURE MAIN OF VGA IS
SIGNAL VGACLK, RESET, lock : STD_LOGIC :='0';
signal SIGNAL_135MHZ : STD_LOGIC:= '0';
COMPONENT SYNC IS
PORT
(
CLK : IN STD_LOGIC;
HSYNC, VSYNC : out std_logic;
R, G, B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
component unsaved is -- PLL Component
port (
pll_0_locked_export : out std_logic; -- pll_0_locked.export
pll_0_outclk0_clk : out std_logic; -- clk
pll_0_refclk_clk : in std_logic := '0'; -- clk
pll_0_reset_reset : in std_logic := '0' -- reset
);
end component unsaved;
BEGIN
inst_pll : UNSAVED port map
(
pll_0_refclk_clk => clock_24,
pll_0_reset_reset => SYS_rst,
pll_0_outclk0_clk => VGACLK, ---CLOCK 65 MHZ
--outclk_1 => SIGNAL_135MHZ, --- CLOCK 135 MHZ
pll_0_locked_export => lock
);
INST_SYNC : SYNC PORT MAP
(
CLK => VGACLK,
HSYNC => VGA_HS,
VSYNC => VGA_VS,
R => VGA_R,
G => VGA_G,
B => VGA_B
);
VGA_CLK_65MHZ <= VGACLK;
END MAIN;
---Sub Program
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY SYNC IS
PORT(
CLK : IN STD_LOGIC;
HSYNC, VSYNC : out std_logic;
R, G, B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END SYNC;
ARCHITECTURE MAIN OF SYNC IS
SIGNAL HPOS: INTEGER RANGE 0 TO 800:=0;
SIGNAL VPOS: INTEGER RANGE 0 TO 525:=0;
BEGIN
PROCESS(CLK,HPOS,VPOS)
BEGIN
IF(CLK' EVENT AND CLK='1') THEN
IF (HPOS = 480 OR VPOS = 285) THEN
R <= (OTHERS => '1');
G <= (OTHERS => '1');
B <= (OTHERS => '1');
ELSE
R <= (OTHERS => '0');
G <= (OTHERS => '0');
B <= (OTHERS => '0');
END IF;
IF(HPOS<800) THEN
HPOS <= HPOS+1;
ELSE
HPOS <=0;
END IF;
IF (VPOS<525)THEN
VPOS <= VPOS+1;
ELSE
VPOS <=0;
END IF;
END IF;
IF (HPOS > 16 AND HPOS < 112)THEN
HSYNC <= '0';
ELSE
HSYNC <= '1';
END IF;
IF (VPOS > 0 AND VPOS < 12) THEN
VSYNC <= '0';
ELSE
VSYNC <= '1';
END IF;
IF ((HPOS> 0 AND HPOS< 160) OR (VPOS>0 AND VPOS< 45)) THEN
R <= (OTHERS => '0');
G <= (OTHERS => '0');
B <= (OTHERS => '0');
END IF;
END PROCESS;
END MAIN;
↧
Quartus ii Simulation option
Dear Sir
I am using Quartus ii 12.0 software.
I am not able to find simulation option under processing menu.
Please help.
Best Regards
Nikhil
I am using Quartus ii 12.0 software.
I am not able to find simulation option under processing menu.
Please help.
Best Regards
Nikhil
↧
↧
the "signed" type i/o in vhd file disapear when i try to add my new component
hi every one;
i write my own component in vhd and try to add it in qsys,
in the component editor, i and my vhd file and click analyze files, it shows 0 errors and 0 warnings.
but in the signals & interfaces tab, i can not find the "signed" i/o in vhd files
like:
S_encoder1_Z_reg_out : out STD_LOGIC_VECTOR(1 downto 0);
S_encoder1_AB_for_interpolation_reg_out : out STD_LOGIC_VECTOR(1 downto 0);
S_encoder1_period_counter_reg_out : out signed(31 downto 0);
the "signed" signal does not appear in signals & interfaces tab, the std_logic and std_logic_vector signals are ok
how can i fix this?
should i have to change the signed to std_logic_vector?
i write my own component in vhd and try to add it in qsys,
in the component editor, i and my vhd file and click analyze files, it shows 0 errors and 0 warnings.
but in the signals & interfaces tab, i can not find the "signed" i/o in vhd files
like:
S_encoder1_Z_reg_out : out STD_LOGIC_VECTOR(1 downto 0);
S_encoder1_AB_for_interpolation_reg_out : out STD_LOGIC_VECTOR(1 downto 0);
S_encoder1_period_counter_reg_out : out signed(31 downto 0);
the "signed" signal does not appear in signals & interfaces tab, the std_logic and std_logic_vector signals are ok
how can i fix this?
should i have to change the signed to std_logic_vector?
↧
NIOS II reset
Hi,
I am connecting the board reset to the NIOS II reset input in the qsys design. The reset vector address is set to the onchip memory. I use the eclipse tool to download my software application. On board reset I see that the application does not execute again. I will have to download the application again to get it working whereas there is no need to program the .sof file on reset. What is the reset requirement of the NIOS II processor. How can I fix this issue.
Thanks & Regards
Bhavya K
I am connecting the board reset to the NIOS II reset input in the qsys design. The reset vector address is set to the onchip memory. I use the eclipse tool to download my software application. On board reset I see that the application does not execute again. I will have to download the application again to get it working whereas there is no need to program the .sof file on reset. What is the reset requirement of the NIOS II processor. How can I fix this issue.
Thanks & Regards
Bhavya K
↧
how to transfer video to my DE2-70 SSRAM
hello,
i have got this code from a friend, which do motion detection from a video.
i compiled the code and programmed the FPGA.
but i couldn't input the video to the device.
as i know the program use SSRAM as the main source for the video.
the code is here: https://drive.google.com/open?id=0B8...3laY2tUYmYxdGM
could you help please!
Thank you!
i have got this code from a friend, which do motion detection from a video.
i compiled the code and programmed the FPGA.
but i couldn't input the video to the device.
as i know the program use SSRAM as the main source for the video.
the code is here: https://drive.google.com/open?id=0B8...3laY2tUYmYxdGM
could you help please!
Thank you!
↧
ALT PLL error
Hi ALL,
I have been trying to simulate a PLL in my design, but for some weird reason i get this error again and again :
** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ps Iteration: 0 Instance: /hdlc_test_tb/uut/HDLC_Testing_entity/TxBuff
# ** Note: Cyclone IV E PLL was reset
# Time: 0 ps Iteration: 4 Instance: /hdlc_test_tb/uut/CLKPLL_MAPING/altpll_component/CYCLONEIII_ALTPLL/M5
# ** Note: Cyclone IV E PLL locked to incoming clock
# Time: 70 ns Iteration: 3 Instance: /hdlc_test_tb/uut/CLKPLL_MAPING/altpll_component/CYCLONEIII_ALTPLL/M5
# ** Error: (vsim-3601) Iteration limit reached at time 710 ns.
My clock input is 50Mhz , and i am trying to get c0 => 25Mhz and c1=> 100Mhz , any clues why my simulation get stuck at 710ns ???
Thanks for reading my post .
Regards ,
I have been trying to simulate a PLL in my design, but for some weird reason i get this error again and again :
** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ps Iteration: 0 Instance: /hdlc_test_tb/uut/HDLC_Testing_entity/TxBuff
# ** Note: Cyclone IV E PLL was reset
# Time: 0 ps Iteration: 4 Instance: /hdlc_test_tb/uut/CLKPLL_MAPING/altpll_component/CYCLONEIII_ALTPLL/M5
# ** Note: Cyclone IV E PLL locked to incoming clock
# Time: 70 ns Iteration: 3 Instance: /hdlc_test_tb/uut/CLKPLL_MAPING/altpll_component/CYCLONEIII_ALTPLL/M5
# ** Error: (vsim-3601) Iteration limit reached at time 710 ns.
My clock input is 50Mhz , and i am trying to get c0 => 25Mhz and c1=> 100Mhz , any clues why my simulation get stuck at 710ns ???
Thanks for reading my post .
Regards ,
↧
↧
FPGA full reconfiguration using MAX II CPLD
Hi all,
I am trying to command full FPGA configuration using MAX II CPLD embedded on the Transceiver Signal Integrity Development Kit with Stratix V.
In the documentation the S5 (connected to the MAX II) is in charge of resetting the logic and initiating FPGA reconfiguration. Is there a way to do it using the push button as documented in the user guide and reference manual ?
If not, do you have some other advice ?
I am trying to command full FPGA configuration using MAX II CPLD embedded on the Transceiver Signal Integrity Development Kit with Stratix V.
In the documentation the S5 (connected to the MAX II) is in charge of resetting the logic and initiating FPGA reconfiguration. Is there a way to do it using the push button as documented in the user guide and reference manual ?
If not, do you have some other advice ?
↧
No buttons MegaWizard? tools-> MegaWizard - no tools?
Hello,
no buttons MegaWizard?
Established Quartus Prime Lite Edition (Free).
My Operating System- WINDOWS 8.1 x64
:confused:
Thanks.
no buttons MegaWizard?
Established Quartus Prime Lite Edition (Free).
My Operating System- WINDOWS 8.1 x64
:confused:
Thanks.
↧
Opencores CAN core with Nios
Hello,
Currently. I am working with MAX10 and CAN core from open cores (http://opencores.org/project,can). At the moment I want to perform only transmission. I have connected a Nios II cpu with the core in a 8051 configuration and I am able to perform some communication between them, but I am still unable to transmit any message. Is there anybody who had already worked with this core who can also share any code with me? I am unable to upload my desgin on the forum cause its too large, but I can transfer the files to anybody who is interesting. Thank you.
Currently. I am working with MAX10 and CAN core from open cores (http://opencores.org/project,can). At the moment I want to perform only transmission. I have connected a Nios II cpu with the core in a 8051 configuration and I am able to perform some communication between them, but I am still unable to transmit any message. Is there anybody who had already worked with this core who can also share any code with me? I am unable to upload my desgin on the forum cause its too large, but I can transfer the files to anybody who is interesting. Thank you.
↧
Verification of Stratix V Hard IP for PCI Express Using Avalon-MM Interface with DMA
Hi, teachers.
I want to ask some questions about the " Stratix V Hard IP for PCI Express Using Avalon-MM Interface with DMA".
1, TX Slave Interface.
Quotes from Avalon-MM 256-Bit Hard IP for PCI Express User Guide.
Page 4.
The TX Slave module propagates 32-bit Avalon-MM reads and writesupstream. Avalon-MM masters can use this slave port to access PCI Expressmemory space. The DMA Controller uses this path to update the DMA statusupstream, including MSI requests.
Page 21.
The TX Slave module translates Avalon-MM master read and write requests to PCIExpress TLPs for the Root Port. The TX Slave Control module supports a singleoutstanding non-bursting request.
According to the quotes, we can write data to TX Slave, then the PCI Express IP converts the data to serial data, then send the serial data to host.
Is my understanding right?
2, Testbench created by Qsys.
I use Qsys to create the testbench for the "Stratix V Hard IP for PCI Express Using Avalon-MM Interface with DMA".
I think in the testbench created by Qsys, the serial data is converted to parallel data. Can you tell me which module in testbench implements Deserializer function?
If my understanding in Question 1 is right, I think I can find the same data I wrote to the TX Slave Interface.
Thanks in advance,
zhang
I want to ask some questions about the " Stratix V Hard IP for PCI Express Using Avalon-MM Interface with DMA".
1, TX Slave Interface.
Quotes from Avalon-MM 256-Bit Hard IP for PCI Express User Guide.
Page 4.
The TX Slave module propagates 32-bit Avalon-MM reads and writesupstream. Avalon-MM masters can use this slave port to access PCI Expressmemory space. The DMA Controller uses this path to update the DMA statusupstream, including MSI requests.
Page 21.
The TX Slave module translates Avalon-MM master read and write requests to PCIExpress TLPs for the Root Port. The TX Slave Control module supports a singleoutstanding non-bursting request.
According to the quotes, we can write data to TX Slave, then the PCI Express IP converts the data to serial data, then send the serial data to host.
Is my understanding right?
2, Testbench created by Qsys.
I use Qsys to create the testbench for the "Stratix V Hard IP for PCI Express Using Avalon-MM Interface with DMA".
I think in the testbench created by Qsys, the serial data is converted to parallel data. Can you tell me which module in testbench implements Deserializer function?
If my understanding in Question 1 is right, I think I can find the same data I wrote to the TX Slave Interface.
Thanks in advance,
zhang
↧
↧
Cyclone III to MAX 10 low level primitives
Hi all,
I have a code for Cyclone III where one LVDS port is defined via low level primitive ALT_OUTBUF_DIFF Primitive.
Now I want to move this code to MAX 10 but realized that MAX 10 is not able to support this type of low level primitives.
Is there any way to reclasify this port to LVDS in MAX 10 code and make it painless as possible??
From what I see here, using LVDS on MAX 10 requires softcore IP as serdes.
Thank you.
Best regards,
Vladan
I have a code for Cyclone III where one LVDS port is defined via low level primitive ALT_OUTBUF_DIFF Primitive.
Now I want to move this code to MAX 10 but realized that MAX 10 is not able to support this type of low level primitives.
Is there any way to reclasify this port to LVDS in MAX 10 code and make it painless as possible??
From what I see here, using LVDS on MAX 10 requires softcore IP as serdes.
Thank you.
Best regards,
Vladan
↧
Hello World
hello,
i'm a Phd student, on my project i will use quartus II. Thus i'm trying to getting started with nios 2.
i installed quartus II v 13.0 on 64 bit ubuntu 15.04.
i tried to run the example of the pdf attached (Hello world) but i don't find the directory nios2eds/examples/verilog.
can
i'm a Phd student, on my project i will use quartus II. Thus i'm trying to getting started with nios 2.
i installed quartus II v 13.0 on 64 bit ubuntu 15.04.
i tried to run the example of the pdf attached (Hello world) but i don't find the directory nios2eds/examples/verilog.
can
↧
Geeting Glitch at the output
I am using A max v CPLD. In my Design I am using 3 counter.
1st counter is getting a 8 MHz Clk and it is used for Clock division purpose. It is Two bit counter. My next counter is 10 bit counter in which after every 8 clock pulse I want to generate chip select signal low.But here after every 8th clock pulse I am getting glitch. Similarly my third counter is of 9 bit in which I have to generate Chip select but getting glitch at the output. How to remove that glitch please help in that issue.
I tried to add constraint to my input clock . By doing this the glitch on my 1st counter is removed. But still getting glitch at output of 2nd and 3rd counter.
1st counter is getting a 8 MHz Clk and it is used for Clock division purpose. It is Two bit counter. My next counter is 10 bit counter in which after every 8 clock pulse I want to generate chip select signal low.But here after every 8th clock pulse I am getting glitch. Similarly my third counter is of 9 bit in which I have to generate Chip select but getting glitch at the output. How to remove that glitch please help in that issue.
I tried to add constraint to my input clock . By doing this the glitch on my 1st counter is removed. But still getting glitch at output of 2nd and 3rd counter.
↧
"+" operation with odd number
hi, everyone, I'm new to verilog. I got a problem when I try to use "+" operator.
I was doing a accumulate sum by add new result to old result. The simulation gives me correct result everytime, but the actual result from FPGA output looks like this:
Current Result: 1 16 7 8 2 5
Previous Result: 0 0 16 22 30 32
Final Result 0 16 22 30 32 36
It is clearly that something wrong with the odd numbers. Here is my code about this three data.
If anyone knows what's wrong or I have confused you please let me know.
I was doing a accumulate sum by add new result to old result. The simulation gives me correct result everytime, but the actual result from FPGA output looks like this:
Current Result: 1 16 7 8 2 5
Previous Result: 0 0 16 22 30 32
Final Result 0 16 22 30 32 36
It is clearly that something wrong with the odd numbers. Here is my code about this three data.
Code:
reg [31:0] final_result;
reg [31:0] previous_result;
reg [31:0] counter;
always @ (*) begin
case(fsm_cs)
FSM_START: begin
counter <= 0;
final_result <= 0;
(to FSN_1)
end
FSM_1: begin
previous_result <= final_result;
(begin some calculation)
end
..........
FSM: begin
counter <= w_result;
final_result <= w_result + previous_result;
(back to FSM_1)
end↧
↧
usb interfacing
hi everyone,
i am new to fpga.
but, i know how to prepare verilog file in quartus2 software. i want use the usb port in altera de2 board for tranfering ang receiving data from pc.
but, i don't know exactly what to do.
please help me.
thank you.
i am new to fpga.
but, i know how to prepare verilog file in quartus2 software. i want use the usb port in altera de2 board for tranfering ang receiving data from pc.
but, i don't know exactly what to do.
please help me.
thank you.
↧
.SOF file not being generated on Lite (free) version
Hello,
I used to use Quartus II (14.1) about a year ago without any problem.
Now I upgraded the computer and downloaded the new version Quartus Prime Lite Edition.
The new version (free) is not generating the .sof file after synthesis and analysis.
No error is reported, same project I used before on the old version of Quartus.
Google says that it might be lack of licensing. But I am using the free version with a ridiculously small project (2 gates).
Ah... My target FPGA is Cyclone IV EP4CE30
Please help!
Tks,
Rodrigo.
I used to use Quartus II (14.1) about a year ago without any problem.
Now I upgraded the computer and downloaded the new version Quartus Prime Lite Edition.
The new version (free) is not generating the .sof file after synthesis and analysis.
No error is reported, same project I used before on the old version of Quartus.
Google says that it might be lack of licensing. But I am using the free version with a ridiculously small project (2 gates).
Ah... My target FPGA is Cyclone IV EP4CE30
Please help!
Tks,
Rodrigo.
↧
Add arrow's opencl data in rootfs
Hi, Sir<br>
I want to add arrow's opencl data in rootfs and build image.<br>
(arrpw's opencl data is arrow-1.0.tar.gz.)<br>
But it's still fail.<br>
Here is my .bb file. Please teach me how to do it.<br>
------------------------------------------<br>
SUMMARY = "Arrow example"<br>
DESCRIPTION = "Arrow example"<br>
SECTION = "example"<br>
LICENSE = "GPLv2"<br>
LIC_FILES_CHKSUM = "file://init_opencl.sh;md5=d2516439455d80030289a8c11bf79c5 a"<br>
<br>
PR = "r0"<br>
<br>
INHIBIT_PACKAGE_STRIP = "1"<br>
<br>
def compress_pkg(d):<br>
if "compress_doc" in (d.getVar("INHERIT", True) or "").split():<br>
compress = d.getVar("DOC_COMPRESS", True)<br>
if compress == "gz":<br>
return "gzip"<br>
elif compress == "bz2":<br>
return "bzip2"<br>
elif compress == "xz":<br>
return "xz"<br>
return ""<br>
<br>
RDEPENDS_${PN} += "${@compress_pkg(d)}"<br>
<br>
SRC_URI = "file://${BP}.tar.gz"<br>
<br>
SRC_URI[md5sum] = "025e00e90a92ecb86349ca8f4fd39551"<br>
<br>
do_install_append(){<br>
mkdir -p ${D}/home/root<br>
cp ${WORKDIR}/${BP}/init_opencl.sh ${D}/home/root<br>
mkdir -p ${D}/home/root/arrow_aocl<br>
cp -r ${WORKDIR}/${BP}/arrow_aocl/* ${D}/home/root/arrow_aocl<br>
mkdir -p ${D}/home/root/opencl_arm32_rte<br>
cp -r ${WORKDIR}/${BP}/opencl_arm32_rte/* ${D}/home/root/opencl_arm32_rte<br>
}<br>
<br>
FILES_${PN} += "${D}/home/root/init_opencl.sh ${D}/home/root/arrow_aocl ${D}/home/root/opencl_arm32_rte"<br>
--------------------------------------------------<br>
Thank you.
I want to add arrow's opencl data in rootfs and build image.<br>
(arrpw's opencl data is arrow-1.0.tar.gz.)<br>
But it's still fail.<br>
Here is my .bb file. Please teach me how to do it.<br>
------------------------------------------<br>
SUMMARY = "Arrow example"<br>
DESCRIPTION = "Arrow example"<br>
SECTION = "example"<br>
LICENSE = "GPLv2"<br>
LIC_FILES_CHKSUM = "file://init_opencl.sh;md5=d2516439455d80030289a8c11bf79c5 a"<br>
<br>
PR = "r0"<br>
<br>
INHIBIT_PACKAGE_STRIP = "1"<br>
<br>
def compress_pkg(d):<br>
if "compress_doc" in (d.getVar("INHERIT", True) or "").split():<br>
compress = d.getVar("DOC_COMPRESS", True)<br>
if compress == "gz":<br>
return "gzip"<br>
elif compress == "bz2":<br>
return "bzip2"<br>
elif compress == "xz":<br>
return "xz"<br>
return ""<br>
<br>
RDEPENDS_${PN} += "${@compress_pkg(d)}"<br>
<br>
SRC_URI = "file://${BP}.tar.gz"<br>
<br>
SRC_URI[md5sum] = "025e00e90a92ecb86349ca8f4fd39551"<br>
<br>
do_install_append(){<br>
mkdir -p ${D}/home/root<br>
cp ${WORKDIR}/${BP}/init_opencl.sh ${D}/home/root<br>
mkdir -p ${D}/home/root/arrow_aocl<br>
cp -r ${WORKDIR}/${BP}/arrow_aocl/* ${D}/home/root/arrow_aocl<br>
mkdir -p ${D}/home/root/opencl_arm32_rte<br>
cp -r ${WORKDIR}/${BP}/opencl_arm32_rte/* ${D}/home/root/opencl_arm32_rte<br>
}<br>
<br>
FILES_${PN} += "${D}/home/root/init_opencl.sh ${D}/home/root/arrow_aocl ${D}/home/root/opencl_arm32_rte"<br>
--------------------------------------------------<br>
Thank you.
↧
