get_service_paths master returns null when system-console invoked remotely over ssh

April 11, 2013, 12:03 pm

≫ Next: Arria II GX VCCIO and Quartus I/O Standard Mismatch

≪ Previous: Have to support ancient product with EPM7032 CPLD USB Blaster problems

Hi,

I have a Qsys system with a JTAG master in a Linux machine. I download the synthesized bitstream over USB JTAG cable into an Altera DE4 board (Stratix IV FPGA) attached to this machine.

Now, I remotely login to this machine using ssh (ssh -XY machinename). I open system console

In system-console when the following command is sourced from the tcl script

set jtag_master [lindex [get_service_paths master] 0];

jtag_master does not getting any value
and fails in successive steps (ie. opening the service etc..)

Strangely this happens only when system-console is remotely invoked (eg. from ssh). If I try running system-console locally and jtag_master gets a valid value. I am using Quartus 12.0.
I can confirm that my JTAG connection works without any issue as jtagconfig returns correctly.

I did try the same command with different numbers as suggested in some of the previous posts ie.
set jtag_master [lindex [get_service_paths master] 1];
set jtag_master [lindex [get_service_paths master] 2]; etc.. with no luck.

Appreciate your inputs,

Thanks
Deepak

↧

Arria II GX VCCIO and Quartus I/O Standard Mismatch

April 11, 2013, 12:26 pm

≫ Next: quartus_cpf generated jic file differs from GUI generated jic file (from sof).

≪ Previous: get_service_paths master returns null when system-console invoked remotely over ssh

In an existing design, I have discovered the following: I am using an Arria II GX FPGA and have the VCCIO for one of the banks tied to +3.3VDC on the baord. The VREF pin for this bank is also connected to +3.3VDC. Within Quartus, I have the "+2.5V" standard selected.

Questions:
1. Is this an acceptable scenario, or could this potentially cause damage to the FPGA?
2. Will the inputs on this bank be subject to the +2.5V input threholds as identified in the device handbook, or the +3.3V thresholds (or some other threshold values)?

↧

quartus_cpf generated jic file differs from GUI generated jic file (from sof).

April 11, 2013, 12:50 pm

≫ Next: Configuration device for Cyclone V

≪ Previous: Arria II GX VCCIO and Quartus I/O Standard Mismatch

Tool: Quartus II 32-bit Version 12.1 Build 177 11/07/2012 SJ Full Version

I've been successfully using the "Convert Programming File" GUI dialog to convert our sof files to jic, for use with an EPCQ256 device. I then saved the Conversion Setup to a cof file, intending to drive the conversion from the Linux command line. However, the command-line generated jic file differs from that generated with the GUI just moments before:

[rrauscher-uut tmp]# ls -lrt armlite_target_AS4_*.jic
-rw-r--r--. 1 root root 33554659 Apr 11 12:37 armlite_target_AS4_GUI.jic
-rw-r--r--. 1 root root 33554659 Apr 11 12:39 armlite_target_AS4_manual.jic
[rrauscher-uut tmp]# md5sum armlite_target_AS4_*.jic
e380eed4cf2e486a4a2589c496cb7c37 armlite_target_AS4_GUI.jic
c4e5a695286f475effea02012ebc242a armlite_target_AS4_manual.jic
[rrauscher-uut tmp]#

The command-line I used is: quartus_cpf --convert ./convert_gui.cof

where convert_gui.cof is the saved Configuration Setup from the GUI. Its contents are here:

<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
<eprom_name>EPCQ256</eprom_name>
<flash_loader_device>5SGXMA7H3</flash_loader_device>
<output_filename>/tmp/armlite_target_AS4_gui.jic</output_filename>
<n_pages>1</n_pages>
<width>1</width>
<mode>13</mode>
<sof_data>
<user_name>Page_0</user_name>
<page_flags>1</page_flags>
<bit0>
<sof_filename>/tmp/armlite_target.sof<compress_bitstream>1</compress_bitstream></sof_filename>
</bit0>
</sof_data>
<version>5</version>
<create_cvp_file>0</create_cvp_file>
<options>
<map_file>1</map_file>
</options>
</cof>

Can anyone tell me why it would be different? The miscompares start a few hundred bytes into the generated jic files.

Thanks,

--rich

↧

Configuration device for Cyclone V

April 11, 2013, 2:50 pm

≫ Next: .pof file checksum

≪ Previous: quartus_cpf generated jic file differs from GUI generated jic file (from sof).

Hello,

I am searching for suitable configuration device for Cyclone V E A9 FPGA. According data sheet the *.rbf file will have size of 102,871,552 bits. Could I use for example S25FL256SAGMFIG01 (256Mb 3V 133MHz Serial NOR Flash) or I need 512 Mb device? My application is cost sensitive, so I need something really cheap.

Thank you!

↧

.pof file checksum

April 11, 2013, 2:53 pm

≫ Next: how to download configure file in the flash by FPGA device itself

≪ Previous: Configuration device for Cyclone V

I have been given a pof file, which I need to submit to a vendor for programming. I need to find out what the check sum is for this pof file.

When I load it into my data io programmer, I get 00000000, which I don't believe. I am running the data io in simulation mode, as I don't have the correct top.

Could someone please look at my file and tell me the checksum, or is there some tool I can use to calculate the checksum?

I don't really want to install the entire development environment

Site wont let me post my email addr, so I will check back here

Thanks all

↧

how to download configure file in the flash by FPGA device itself

April 11, 2013, 7:45 pm

≫ Next: What is Altera postion about USB Blaster Clones?

≪ Previous: .pof file checksum

there is a problem of how to download configure file in the flash by FPGA device itself。
there is my opinion as below：
1. I have already designed a SPI driver which can read and write the EPCS4 .
2. Use this driver the write the configure data in the EPCS4，
3. RePower-ON the FPGA device ,then to achieve update the new configure data by itself

my question.
1. Is this way OK for update Code by itself?
2. but there is a problem of the configure file(.rbf or .hexout),which was declared OK for configure by third microprocessor.
i have read out all the data in the EPCS4 from 000000 to the end ,and compare those data with .rbf file showing data,then i found there is not only the LSB load first different but also same addresss load different data,so i think the configure data was loaded in a complex way which i don't know.

3. how does third mircoprocessor to load the data in EPCS4?
4. what is the structure of those configure file

↧

What is Altera postion about USB Blaster Clones?

April 11, 2013, 9:27 pm

≫ Next: Diff_SSTL_2 class 2 in IBIS model for EP4CE55

≪ Previous: how to download configure file in the flash by FPGA device itself

Hello,

I am developing an Cyclone IV development kit and want to embed an USB Blaster compatible circuit (not the same hardware). Is there any license requirement or legal problem regarding this? The USB Blaster will be used just to program and debug the Existing FPGA on the board and wont enable to program external ones.

Best regards,

LR

↧

Diff_SSTL_2 class 2 in IBIS model for EP4CE55

April 12, 2013, 12:50 am

≫ Next: web server on FPGA

≪ Previous: What is Altera postion about USB Blaster Clones?

Hello!
I have downloaded IBIS for Cyclone 4. But there are no any models for dsstl2c2_ciop_d16m and dsstl2c2_cion_d16m. Where I could find models for this pins? Or maybe it is possible to use another models from this IBIS-file?

↧

web server on FPGA

April 12, 2013, 2:05 am

≫ Next: delay generation problem

≪ Previous: Diff_SSTL_2 class 2 in IBIS model for EP4CE55

Hi,
i want to implement web server application on the FPGA but i don't really know how to proceed.i'd like to ask which protocol i should use(http, ftp, tftp..) and even how to use it if i will read real time data (images from the SDRAM).
is there someone who tried it and can help me?
thanks in advance..

mira.

↧

delay generation problem

April 12, 2013, 3:56 am

≫ Next: Error: Eclipse (Code Stuck at printf function) Incompatible 2 value with TX_CMD_STAT

≪ Previous: web server on FPGA

hi,
i have done a vhdl project with quartus and call it with nios,
I don't have good result do to a delay generation.
please how can i repair my work and have this result after this delay??
thank you

↧

Error: Eclipse (Code Stuck at printf function) Incompatible 2 value with TX_CMD_STAT

April 12, 2013, 4:45 am

≫ Next: Importing IP into SPOC builder

≪ Previous: delay generation problem

InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
prep_tse_mac 0
Your Ethernet MAC address is 00:07:ed:11:83:04
prepped 1 interface, initializing...
[tse_mac_init]
INFO : TSE MAC 0 found at address 0x0b482000
INFO : PHY Marvell 88E1111 found at PHY address 0x10 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link not yet established, restart auto-negotiation...
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : PHY[0.0] - Link established
INFO : PHY[0.0] - Speed = 100, Duplex = Full
OK, x=0, CMD_CONFIG=0x00000000
[tse_mac_init] Error: Incompatible 2 value with TX_CMD_STAT register return TxShift16 value.
init error -11 on net[0]
mctest init called
IP address of : 192.168.1.207
Created "Inet main" task (Prio: 2)
Created "clock tick" task (Prio: 3)

Simple Socket Server starting up

Initillize the Enhanced Interrupt..
Enhnace interrupt ENABLED, Return value = 0
Created "simple socket server" task (Prio: 4)
RS232 Port Open....!!

----Ready to Receive Interrupt----

#Synchronous Data received...!!

and then code stuck after displaying "#Synchronous Data received...!!"

Code:





void SSSSimpleSocketServerTask()

{

    unsigned int    LPktCount    =    0;

    unsigned int    Count        =    0;

    unsigned int    DataCount     =    0;

    unsigned char    ImgData        =    0;

    unsigned int    test        =    0;



//--------------------------Receive From RS-422 Port @ 1 mbps-------------------------------------------

      printf("\n\t\t----Ready to Receive Interrupt----\n");

      while(1)

        {

              do

              {

                    if( edge_capture)        //w.r.t. clock or LOAD Pulse from "sync_detect"

                      {

                        edge_capture = 0;

                        ImgBuff[LPktCount][Count++] = IORD_ALTERA_AVALON_PIO_DATA(DATA_BASE);

                        }

                            if(Count    ==    PktSize-1)

                            {

                            Count    =    0;

                            LPktCount++;

                            }

              }while(LPktCount    !=    (PktCount+1));



 

              printf("\n\t#Synchronous Data received...!!"); //Code stuck at this Line 

//----------------------Sending to RS-232 -------------------------------------------------------

              printf("\n\t#Sending Data at RS232 Port at 115kbps...\n");



                       Xstart = 0;

                        Ystart = 0;

                       LPktCount = 0;



                        printf("\n\t# Send Sync Word..");

                        for(Count = 0; Count<=2;Count++)

                            {

                            fprintf(fp,"%c",strt_sync[Count]);

                            printf("\t%d",strt_sync[Count]);

                            }





                            for(LPktCount = 0+Ystart; LPktCount<mPktCount;LPktCount++) //

                            {

                                for(DataCount = 0; DataCount<mPktSize;DataCount++)

                                     {

                                    ImgData    =    ImgBuff[LPktCount][DataCount];

                                    fprintf(fp,"%c",ImgData);

                                     }

                                     printf("#");

                            }





        }





}

Attached Images

Console View.jpg (219.7 KB)

↧

Importing IP into SPOC builder

April 12, 2013, 4:49 am

≫ Next: PCIe RootPort+EndPoint Simulation

≪ Previous: Error: Eclipse (Code Stuck at printf function) Incompatible 2 value with TX_CMD_STAT

Hi all,
I'm currently working on building an sopc builder and using on cyclone III target device.
I have written a simple counter program to glow the LED's to familiarize myself with SOPC builder.
I imported my IP into the component editor, added the HDL file and have to connect signals in my design to an interface and signal type.
My signals are
1. Clk (input)
2.reset (input)
3.Display (output)

So i connected my clk to a clock_sink.
But none of the other interfaces and signal types available seem to match my requirement, because I'm driving reset externally using a switch. And outputs are connected to LED's. I tried using conduit interface and export the signals but that does not work.
Help needed.
Thank you.

↧

PCIe RootPort+EndPoint Simulation

April 12, 2013, 7:11 am

≫ Next: Test Pattern Generator ( from VIP Suite ) seems not to be functioning normally.

≪ Previous: Importing IP into SPOC builder

I have designed two systems - a RootPort and an EndPoint on two different PCBs, each with a NIOS II. Now, I am trying to do system-level simulation with both designs in one testbench.
My Endpoint design does not use a DMA in the normal sense. I managed to simulate the RooPoint example fine, but trying to adapt it to my requirement proved very difficult making it useless.
The test driver is very difficult to follow because it uses the PIPE access and is not general purpose enough.
I would like to do the RP and EP configuration using the PIPE method using two actual designs and the rest via the pcie_rx and pcie_tx wires.
Has anyone done system-level simulation with two real design (not BFM + real)?

P.S. The RP works fine in HW while the EP only responds to enumeration but not memory write/read TLP.

S.

↧

Test Pattern Generator ( from VIP Suite ) seems not to be functioning normally.

April 12, 2013, 9:28 am

≫ Next: Audio in the DE2-70

≪ Previous: PCIe RootPort+EndPoint Simulation

Test Pattern Generator ( from VIP Suite ) seems not to be functioning normally in Quartus 12.1 sp1.
If generated by MegaWizard it does not produce a valid VHD.
The compilation results in "Error (12007): Top-level design entity "TPG" is undefined".

In the same way I tried Clocked Video Output ( also from VIP Suite ). Its OK.

Does it seem to be a bug in Test Pattern Generator or am I missing smth?

Attached Files

TPG.vhd (3.2 KB)
TPG_bb.v (1.9 KB)

↧

Audio in the DE2-70

April 12, 2013, 9:30 am

≫ Next: Strange error with QDR-II+ IP

≪ Previous: Test Pattern Generator ( from VIP Suite ) seems not to be functioning normally.

I am working with video work in the DE2-70 specifically commercial detection. The idea is that a tv show will be playing then when a commercial comes on it will get muted and we will see a black screen come up. Now I am confused as to how we can mute audio in the DE2-70, does anyone have an idea of how I can do it using verilog and quartus?? Thank you

↧

Strange error with QDR-II+ IP

April 12, 2013, 9:38 am

≫ Next: Build Error using template: /HAL/src/alt_main.c:154: undefined reference to `main'

≪ Previous: Audio in the DE2-70

We're using the QDR-II+ controller IP on the Stratix V 5SGSED8N. We'd like to have a single controller that can access 4x 144 Mbit QDRs (i.e. 576 Mb of accessible memory). Due to pin count issues, we'd like to do this with 4, 18-bit wide devices, like the Cypress CY7C2663KV18. So our 4-device wide interface will have 72-bit wide data interfaces.

Using the megawizard in quartus 12.1 64 bit, I've generated IP that appears to do this and a basic implementation. In the megawizard, I selected a device width of 36 using x36 emulated mode, and chose a device width of two. This does generate a 72-bit wide data interface. However, it won't place and route. It gives the cryptic error message:

Code:

Error (332000): ERROR: Argument <pin_object> is an empty collection. Specify one that is a non-empty collection.





    while executing

"get_pin_info -name $pin_info"

    ("foreach" body line 139)

    invoked from within

"foreach { inst } $instances {

    if { [ info exists pins ] } {

        # Clean-up stale content

        unset pins

    }

    array set pins $qdr72_p0_ddr_db($inst)





    set ..."

    (file "qdr72/qdr72_p0.sdc" line 171)

which I assume are related to a pair of these Critical Warning messages:

Code:

Critical Warning: qdr72_p0.sdc: Failed to find CPS output for pin

an archived version of the project is attached.

Has anybody seen this error before? What does it mean? How can I get around it? Is what we're trying to do actually supported by the IP (4x18)?

Thanks in advance :)

Attached Files

QDR72.qar (535.4 KB)

↧

Build Error using template: /HAL/src/alt_main.c:154: undefined reference to `main'

April 12, 2013, 10:12 am

≫ Next: Signal Tap II - Invalid JTAG Configuration (using USB Blaster) (Cyclone IV)

≪ Previous: Strange error with QDR-II+ IP

Hi,

I'm attempting to use the Nios processor for the first time since i've upgraded to Quartus version 12.1 on a Windows 7 machine. The Nios that comes with this version of Quartus is..Version: Indigo Service Release 2. Build id: 20120216-1857

The error i get is:

Code:





**** Build of configuration Nios II for project Hello_Led_12_04_13 ****

......

.....    (Plenty of build code)

.....

....

[BSP build complete]

Info: Linking Hello_Led_12_04_13.elf

nios2-elf-g++  -T'../Hello_Led_12_04_13_bsp//linker.x' -msys-crt0='../Hello_Led_12_04_13_bsp//obj/HAL/src/crt0.o' -msys-lib=hal_bsp -L../Hello_Led_12_04_13_bsp/   -Wl,-Map=Hello_Led_12_04_13.map   -O0 -g -Wall   -EL -mno-hw-div -mhw-mul -mno-hw-mulx  -o Hello_Led_12_04_13.elf  -lm 

../Hello_Led_12_04_13_bsp/\libhal_bsp.a(alt_main.o): In function `alt_main':

C:\altera\12.1\WorkingArea\BiggerNios\software\Hello_Led_12_04_13_bsp/HAL/src/alt_main.c:154: undefined reference to `main'

collect2: ld returned 1 exit status

make: *** [Hello_Led_12_04_13.elf] Error 1





**** Build Finished ****

The code i am using is an unchanged stock template that comes with the installation. Which is the stock Hello LED template.

Code:

/************************************************************************** * Copyright (c) 2004 Altera Corporation, San Jose, California, USA.      *

 * All rights reserved. All use of this software and documentation is     *

 * subject to the License Agreement located at the end of this file below.*

 *************************************************************************/

/******************************************************************************

 *  DANGER ** WARNING ** Please read before proceeding! ** WARNING ** DANGER  *           

 ******************************************************************************

 *

 * This program is an example of a "free-standing" C application.  If you 

 * modify this example and try to call C library functions such as printf, they 

 * will NOT work unless you explicitly initialize the system, such as in the

 * hello_alt_main software template.  Please see below for details.

 *

 * Description

 * ************* 

 * A very minimal program that simply shifts an LED back and forth.

 * 

 * Requirements

 * **************

 * According to the ANSI C standard, freestanding programs "own" the hardware, 

 * and cannot rely on system-services or device-drivers being initialized prior

 * to program-start. A freestanding program is responsible for initializing all

 * hardware devices, device-drivers, and system-services. Many embedded 

 * programs are, by nature, freestanding. The author relinquishes any illusion 

 * of running their program on a workstation.

 * 

 * This example is a freestanding program because it's entry point is the 

 * function:

 * 

 *    void alt_main (void)

 * 

 * As opposed to "main()" as a "hosted" application would (see the 

 * "hello_world" example). 

 * 

 * Upon entry to alt_main():

 * - The CPU's caches (if any) have been initialized.

 * - The stack-pointer has been set.

 * - That's all. The rest is up to you.

 * 

 * If you modify this example and try to call C library functions such as 

 * printf, they will NOT  work unless you explicitly initialize the system.

 * If you wish to use C library calls, it is strongly suggested you start 

 * with the hosted hello_world template which uses main() as it's entry 

 * point.

 * 

 * On the other hand, if you want to write a program that gets-in even 

 * earlier, you will need to provide your own assembly-language machine-setup 

 * code by defining the symbol "_start". Any definition of _start in your 

 * directory will override the library definition. You can find source code 

 * for the Nios II library _start here:

 * 

 *   <NiosII-Kit-Install-Dir>/components/altera_nios2/HAL/src/crt0.S

 * 

 * This software example requires a system with a PIO peripheral named 

 * "led_pio".  The software example will run on the following hardware 

 * examples:

 * 

 * Nios Development Board, Stratix II Edition:

 * -  Standard

 * -  Small

 * -  Full Featured

 *

 * DSP Development Board, Stratix II Edition:

 * -  Standard

 * -  Small

 * -  Full Featured

 *

 * Nios Development Board, Stratix Edition:

 * -  Standard

 * -  Small

 * -  Full Featured

 * 

  * Nios Development Board, Stratix Professional Edition:

 * -  Standard

 * -  Small

 * -  Full Featured

*

 * Nios Development Board, Cyclone Edition:

 * -  Standard

 * -  Small

 * -  Low Cost

 * -  Full Featured

 * 

 * Peripherals Exercised by SW

 * *****************************

 * The hello_led.c program simply shifts an 8-bit variable back and forth, 

 * writing the variable's value to the system's LED PIO peripheral on every 

 * iteration.

 * 

 * Software Files

 * ****************

 * hello_led.c - Main C file that contains the simple led manipulation routine.

 * 

 */





#include "system.h"

#include "altera_avalon_pio_regs.h"

#include "alt_types.h"





  /* 

   * This is a freestanding application, so we want to use alt_main

   * as the entry point.  However, if the debugger is run on this

   * application, it will try to set a breakpoint at main, which 

   * the application does not contain.  The below line creates an

   * alias so the debugger is able to set a breakpoint at main, 

   * yet the application retains alt_main as it's entry point.

   */





int main (void) __attribute__ ((weak, alias ("alt_main")));





  /* 

   * Use alt_main as entry point for this free-standing application

   */





int alt_main (void)

{

  alt_u8 led = 0x2;

  alt_u8 dir = 0;

  volatile int i;

     

  /* 

   * Infinitely shift a variable with one bit set back and forth, and write

   * it to the LED PIO.  Software loop provides delay element.

   */

  while (1) 

  {

    if (led & 0x81) 

    {

      dir = (dir ^ 0x1);

    }





    if (dir) 

    {

      led = led >> 1;

    } 

    else 

    {

      led = led << 1;

    }

    IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE, led);





    /* 

    * The delay element in this design has been written as a while loop

    * to avoid confusing the software debugger.  A tight, one line software

    * delay loop such as:

    *   for(i=0; i<200000; i++);

    * can cause problems when it is stepped through using a software debugger.

    * The while loop below produces the same behavior as the for loop shown 

    * above, but without causing potential debugger problems.  

    */

 

    i = 0;

    while (i<200000)

      i++;

  }





  return 0;

}





/******************************************************************************

*                                                                             *

* License Agreement                                                           *

*                                                                             *

* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *

* All rights reserved.                                                        *

*                                                                             *

* Permission is hereby granted, free of charge, to any person obtaining a     *

* copy of this software and associated documentation files (the "Software"),  *

* to deal in the Software without restriction, including without limitation   *

* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *

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This is my SOPC build. Which should have the PIO periipheral but for this error, shouldn't be an issue.

This shows that my SOPC, builds successfully.

And this the directory of the Nios project.

So the question is, why do i get the error that i do? And how do i fix it?

Any help is much appreciated.

↧

Signal Tap II - Invalid JTAG Configuration (using USB Blaster) (Cyclone IV)

April 12, 2013, 3:43 pm

≫ Next: D Flip Flop

≪ Previous: Build Error using template: /HAL/src/alt_main.c:154: undefined reference to `main'

Hi, I'm trying to use SignalTap in the Quartus II IDE and after setting up USB Blaster according to some online tutorial, (it seems to be working in the sense that the "Hardware Setup" tab identifies and allows me to select "USB-Blaster [4-2]" as the device) and programming the FPGA with the .sof file successfully, when I try to run "Autorun Analysis" in SignalTap II, all it says "Invalid JTAG Configuration" (see uploaded image). I have tried doing a couple of various things to try to fix the error but none have actually been succesful.

I'm pretty new to the Quartus Software as well as SignalTap so if I need to provide more information to further explain the situation I am experiencing let me know.

Thanks

screenshot.jpg

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↧

D Flip Flop

April 12, 2013, 3:52 pm

≫ Next: PLL Issues

≪ Previous: Signal Tap II - Invalid JTAG Configuration (using USB Blaster) (Cyclone IV)

Hi All,

I created a simple VHDL D flip flop but saw strange results on the logic analyzer. The code is as follows:

Code:

df:process(reset,clk) begin



     if(reset='1') then 

           Q<=0;

      else

           if(clk'event AND clk='1') then

                   if(A AND B) then

                      Q<=D;

                    else

                      Q<=Q;

                    end if;

             end if;

       end if;

end process;

Where reset,clk, A, Q, D, and B are standard logic vectors. When I view what is happening on the logic analyzer, I see that Q always follows the value of D, regardless of the value of A and B. I'm new to VHDL but what from what I understand Q should never be updated with D unless A and B are true on a clock edge.
I also got a compiler warning in Quartus 12.1 about not having D in my sensitivity list.

Is there something wrong with this code?

Thanks,
DigitalEE

↧

PLL Issues

April 13, 2013, 1:14 am

≫ Next: Default latched outputs values

≪ Previous: D Flip Flop

Hi,

In my code, I need to do 10MHz to 50MHz PLL and transfer the output to about 10 internal modules. Is it customary and synthesizable? Is there any restriction for Altera PLL fun out

Can I use direct PLL conversion from 10MHz to 50MHz or should I use PLL to about 100MHz and then use Freq divider to 50MHz. What is your recommendation?

Thanks,
Idan

↧

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