Hello, quick question for everyone. I've been looking over the documentation on the Cyclone V PCIe hard IP and not sure if you need to buy a Megafunction to implement a PCIe link on the Cyclone V? The documentation states, "The PCIe hard IP consists of the MAC, data link, and transaction layers". What exactly is "hard IP"? I found the following in the documentation, "The Cyclone® V PCIe hard IP operates independently from the core logic" what is this and how is it different than lets say implement a PCIe link on a Stratix IV fpga?
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