Hi there people, I'm studying VHDL programing and i'm getting stuck on this question and i have a examination coming up soon, so i'm stressing a little.
My question is.
A 5-bit signed number (two complement) is read into a machine on the push and release of an active low ley. negative values are converted into positive magnitude form and even valued number are ignored. When 8 odd valued numbers have been entered, the machine displays the average value of the set along with a ready indicator. The machine then halts and repeats the process on activation of an asynchronous master reset of active low.
COuld someone please help me write a register transfer language sequence. Could you please show me step by step so i understand where is start and the process. I would love to be shown how its done and not just here the answer so i get the question.
kind regards
My question is.
A 5-bit signed number (two complement) is read into a machine on the push and release of an active low ley. negative values are converted into positive magnitude form and even valued number are ignored. When 8 odd valued numbers have been entered, the machine displays the average value of the set along with a ready indicator. The machine then halts and repeats the process on activation of an asynchronous master reset of active low.
COuld someone please help me write a register transfer language sequence. Could you please show me step by step so i understand where is start and the process. I would love to be shown how its done and not just here the answer so i get the question.
kind regards