Hi,
I do my first steps with QSYS and I am building a NIOS II processor with on-chip RAM and some peripherals like SPI and PIO interfaces. I divided my design into 2 sub-designs; one sub-design has several SPI-interfaces and a PIO; the top level block has the NIOS controller, a timer and the on-chip RAM.
in my sub-design block I am using a Avalon MM bridge, a clock bridge and a reset bridge. These work fine, but my problem are the IRQ signals.
The SPI interfaces (in the sub-block) are IRQ senders and the NIOS processor (in the top-level block) is the IRQ receiver. How do I connect them? How do I route the IRQ signals from the sub-block to the top-level block? I cannot export the IRQ sender signals and I cannot use the IRQ bridge offered by QSYS. The IRQ bridge seems to be usable if the IRQ receiver is in a sub-design block, but for me it does not support multiple IRQ sender in a sub-block.
Do I need to write my own IRQ bridge? If yes, is the IRQ bridge simply a port map or do I need to use registers to get the same latency as the Avalon MM bridge? Any suggestions?
If nothing helps I will return to a flat design. This seems to work without a problem. At least you can route the IRQs easily from the SPI ports to the NIOS processor in a flat design.
I do my first steps with QSYS and I am building a NIOS II processor with on-chip RAM and some peripherals like SPI and PIO interfaces. I divided my design into 2 sub-designs; one sub-design has several SPI-interfaces and a PIO; the top level block has the NIOS controller, a timer and the on-chip RAM.
in my sub-design block I am using a Avalon MM bridge, a clock bridge and a reset bridge. These work fine, but my problem are the IRQ signals.
The SPI interfaces (in the sub-block) are IRQ senders and the NIOS processor (in the top-level block) is the IRQ receiver. How do I connect them? How do I route the IRQ signals from the sub-block to the top-level block? I cannot export the IRQ sender signals and I cannot use the IRQ bridge offered by QSYS. The IRQ bridge seems to be usable if the IRQ receiver is in a sub-design block, but for me it does not support multiple IRQ sender in a sub-block.
Do I need to write my own IRQ bridge? If yes, is the IRQ bridge simply a port map or do I need to use registers to get the same latency as the Avalon MM bridge? Any suggestions?
If nothing helps I will return to a flat design. This seems to work without a problem. At least you can route the IRQs easily from the SPI ports to the NIOS processor in a flat design.
