Parallel Flash Loader For MAX II .

Hi Everyone,

I am using the Parallel flash loader for CPLD to configure an FPGA using an on board NOR flash.
I have been able to generate the IP by following AN478 and AN386.

I have instantiated a flash_inst from my CPLD top file. The Flash QIP is called from the flash_inst.
My question is , do I have to generate the test bench for the flash_inst, which is calling the Flash IP?

Thank you in advance.