Hello,
I have an application where I need to perform 1024 point FFTs on multiple channels simultaneously. I'm gauging the capabilities of the UG-FFT IP Core while also narrowing down which Altera FPGA I will use for the task.
This will be the first time I'm using an FPGA to do FFTs so I'd like to make sure I'm interpreting the information correctly from the user guide here: https://www.altera.com/en_US/pdfs/li.../ug/ug_fft.pdf
The first question is maybe a silly one but it's not clear to me. In the table below, (table excerpt from user guide), what is the fmax column referring to?
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Is this the maximum clock rate at which I can clock the FFT Core for the particular device? Or is it the maximum FFTs-per-second I can compute using the particular device at it's maximum clock rate? Or something else?
Second question has to do with interpreting the logic resource requirements. So for example, let's say I need to compute ten (10) FFTs in parallel as quickly as possible and I want to do it with an Arria V device and using the 4-engine buffered burst option from the table above. Am I correct in assuming the total resources would be each column multiplied by 10? So for my example of 10 parallel FFTs with an Arria V, would my total ALM requirement be 44,850, (10 * 4,485)? And so on for the other resources?
Thanks in advance!
I have an application where I need to perform 1024 point FFTs on multiple channels simultaneously. I'm gauging the capabilities of the UG-FFT IP Core while also narrowing down which Altera FPGA I will use for the task.
This will be the first time I'm using an FPGA to do FFTs so I'd like to make sure I'm interpreting the information correctly from the user guide here: https://www.altera.com/en_US/pdfs/li.../ug/ug_fft.pdf
The first question is maybe a silly one but it's not clear to me. In the table below, (table excerpt from user guide), what is the fmax column referring to?
Is this the maximum clock rate at which I can clock the FFT Core for the particular device? Or is it the maximum FFTs-per-second I can compute using the particular device at it's maximum clock rate? Or something else?
Second question has to do with interpreting the logic resource requirements. So for example, let's say I need to compute ten (10) FFTs in parallel as quickly as possible and I want to do it with an Arria V device and using the 4-engine buffered burst option from the table above. Am I correct in assuming the total resources would be each column multiplied by 10? So for my example of 10 parallel FFTs with an Arria V, would my total ALM requirement be 44,850, (10 * 4,485)? And so on for the other resources?
Thanks in advance!
