stratix V Native phy Delay.
Hi all, I am using a Stratix V native phy transceiver for my project where I have proprietary PCS block sitting next to PMA hard block of the stratix v transceiver. Now I want to calculate delay...
View ArticleRetrieval of Factory Image data in EPCS64 Flash on DE2-115 Board
Hi, Accidently, I programmed the EPCS64 with custom Programmable Object file(.pof) having start address 0x0 in auto mode and didn't check the address whether it is in application region or factory one...
View Articlenon-blocking AvMM reads
Hi, I have observed that when user application tries to read from a non-existing address the uC hangs, but when doing the same with memory viewer in debug mode, it doesn't. I would assume the debugger...
View Articlequartus main display
Can anybody advise where I find description of the Quartus II main display? To be explicit, I want to know the meaning of the one-row window in the icon bar, just between the "Redo" button and "Project...
View ArticleEthernet not work with Linux on HPS
hello, I copied the files from rocketboards to the sd card and configure all of the switchs and jumpers. My linux boot but I never succeeded to connect the board on the network to test the web...
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demodulator with altera megafunction
hi, i've to realize a i-q demodulator for low frequencies signals with the classical scheme iq.jpg The input signal is a 1,3Hz am modulated with a 50hz frequency for a logic HIGH. now i want to...
View ArticleUSB Hub issue
Hi, I am working on USB Hub on Altera Cyclone V. All ports of the hub are getting detected by the controller. But at a time only one port is working, I mean only one high speed device which is...
View ArticleQsys - Base Address Problem
Hello everyone, i have created a qsys-system with a state machine working as an avalon memory mapped master and a pio working as an avalon memory mapped slave. The Master uses 32bit for addresses and...
View Articleflash memory with system console
Hello everyone, I created a system of image processing on Quartus without processor Nios: JTAG to avalon Master "replace" the processor and I can send commands by System console (.tcl). I want to load...
View ArticleLinker Script : Nios II + DDR3 and On-Chip RAM
Hi, I want read/write DDR3 using Nios II. In my Qsys system, I have included Nios II, JTAG UART, On-Chip RAM and DDR3 Controller. I am using On-Chip RAM as my program RAM (connected to Instruction...
View ArticleStratix V Advanced Systems Development Kit clock problem
Hi, my instantiated altera pll goes out of lock periodically when I use the 50MHz clock svb_clk_50 (FPGA 2). When I use the 100 MHz clock input svb_clk_p as pll clock reference everything is working...
View ArticleTest pattern generator from the Altera VIP suite
Hi, there seems to be a problem with the test pattern generator in conjunction with Quartus 13.1. When I run elaboration Quartus fails because the TPG component does not contain any ports. When I run...
View ArticleI have replaced a EP3C5F256I8N with a EP3C10F256I7N
I have replaced a EP3C5F256I8N with a EP3C10F256I7N. Question #1. Is this a "drop in replacement"? Question #2 Do I need to change the program to let it know that it is going into the EP3C10? Thanks O.G.
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Help setting Cyclone III pins to 3.3V
Hello, I am trying to set two pins on the Cyclone III I'm using (EP3C120F780C7N) to work at 3.3V. I'm developing a custom slave I2C controller and the I2C bus will be 3.3V. I changed the pin...
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Unable to get 64 bit PCIe Address Headers ( only 32bit addresses are possible )
Hi. We have to a PCIe HIP Root Port in a Cyclone V FPGA. We need to use 64 bit addressing to support the needs of our project. We are using the Avalon-MM interface connection , x 4 lane and are...
View ArticleProblem with SDRAM: works fine on Cyclone II but not on Cyclone IV
Hi forum, This problem is getting me crazy! I have two boards, both with an Alliance AS4C8M16S-6TIN SDRAM, one has a EP2C5T144C8N and the other a EP4C15E22C7N. I'm using Qsys SDRAM controller to...
View ArticleLinux 3.9.0 Ftrace function_graph not working
Hello, I'm using Arria V SoC developpement board with HPS (2x Cortex A9) core. I'm currently using the Linux Kernel 3.9.0 sources from RocketBoards.org . I would like to use ftrace tool in order to...
View ArticleQuartus .SOF Missing
Hi, I am new user of Cyclone SOC and i have designed a simple project for LEDs, it is working well but when i have tried to program on my FPGA board the .SOF file was missing. I think i could not find...
View ArticleWhat fpga is best suited for image processing ? which is less cost
What fpga is best suited for image processing ? which is less cost and good performance
View ArticleGigabit Ethernet Interface ( Marvell 88E1111) with Cyclone V help!!
I builded a project(Gigabit Ethernet Interface) used cyclone IV ,it works well on 1000M bps 100Mbps 10Mbps;(TSE+KSZ9031) I change the project and now it can wok on cyclone V(5CGTFD9E5F35C7)(TSE+Marvell...
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