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Bitbake Output Packages
Hey! Referring to [1], I was wondering if it is possible to run the bitbake process and only have the green field as output. I would like to have only packages as output and then, later, I would run...
View ArticleHow to use UFM IP of Altera MAX10
Hi to all, I need to use user flash memory of MAX10 FPGA. I have some questions; 1. Do I need to use NIOS II processor (as Master) to access the altera on chip flash? 2. Is there any other option to...
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DDR3 on Cyclone V E
Hi I would like to connect the MT41J128M16JT-125 with the uniPHY to my Cyclone V E as a hard memory interface. My clk_0 is 50MHz and the Systemclock is 80MHz. I connected the cmd and fifos from the...
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Error instaling Cyclone V device support for Quartus Web Edition
Hi, I have downloaded Quartus II web edition, installed it succesfully, but i have encountered an error trying to add Cyclone V support (cyclonev-15.0.0.145.qdz file) See attachment. Any tips ? Thanks,...
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boot from S25FL512S
Hi all, I try to boot from QSPI Flash (S25FL512S) but I am having some difficulties. I have the same DDR3 as altera cyclone v soc board + two QSPI S25FL512S connected to the hps side. Input clock for...
View ArticleUsing AXI on Stratix FPGA
Hi, I want to use a AXI master and slave in design. How do I use the AXI ip core provided in quartus? I dont want to create a completely new design, that is why creating a new design (and including the...
View ArticleDeveloping a DVI to USB video capture program
Hi guys, I'm developing a DVI grayscale video capture and outputting the stream of video serialized via USB. Since the normal USB won't handle data transmission at 800x600 resolution, 139 MHz clock...
View ArticleSOC priority rule question
Hello, I have a question regarding SOC rules and their priorities. I use on my design a double clocked memory block. The logic runs at clock1x = 100 Mhz and the memory block uses clock2x = 200 Mhz....
View ArticleDoes EDS 13.1 deferent with EDS14.1?
I uses ds-5 13.1 but the Altera SOC embedded design suite user guilde is aboult the verson 14.1. I find something deferent,the toochains just one ARM compiler....and i can't debug with this...
View ArticleUser Auto-Refresh Conduit with hard memory Controller. Strange request...
Hi all, I have an FPGA application which needs the DDR3. I am able to write and read through the MPFE (Multi-Port Front End) but I have some criticial timing therefore I want to handle the refresh by...
View ArticleHow to make Master module to access the avalon MM slave peripherals
Hi, I am writing code for making the master module to access the avalon MM slave peripherals (e.g. UFM and ADC). But first I need to know that is there any IP available to access these modules (UFM and...
View ArticleFpga2Hps Bridge
Hello there, I am trying to get acces to the EMAC registers from the FPGA. Currently i'm using the fpga2hps bridge with an address span extender. In the logic analyser, i can see that the right address...
View ArticleTrigger and counter.
Hi, I'm trying to implement a counter that counts down when it recieves a trigger pulse from the hardware (in this case, it's a short burst of AC, in the order of a few hundred µs), which keeps an LED...
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UF-FFT, FFT IP Core, interpreting performance and resource utilization
Hello, I have an application where I need to perform 1024 point FFTs on multiple channels simultaneously. I'm gauging the capabilities of the UG-FFT IP Core while also narrowing down which Altera FPGA...
View ArticleModule avalon mm slave and master
I need a example of a module avalon mm that is master and slave. Or how can I build one.
View ArticlePCIe Force Gen1 Link
I've built a design around a Stratix V and the Avalon-ST Hard IP Core. The device is designed for Gen3x8 which is working fine. I now want to connect the design to a laptop via a Gen1x1 ExpressCard...
View ArticleStrange bus failure
I am using Quartus 2 schematic entry for my project. I have designed an RS232 uart and baud rate generator. On the board, there is a 4 digit LED display. At the top level, if I connect the output bus...
View ArticleDE1 / Cyclone II with Quartus II (v15)?
Hello everyone! I just dug out a DE1* board I used for some projects during college, hoping to use it for an upcoming DIY project. Downloaded and Installed the latest Quartus II software, only to find...
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Cyclone II LVDS termination on DE2
hey guys, I the plan is to use the Terasic DE2 LVDS lines to receive serial data from an ADC. The Cyclone II device handbook (figure 11-3) says that the LVDS receiver line should terminate with 100ohm...
View ArticleAccessing SRAM from NIOS and Verilog Module
Hi, I have implemented the Web Server example on the DE2-115 and modified it a bit to send data over ethernet to the DE2-115 board and store it in the SRAM. This data is around 1Mbit . Next I want to...
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