Kit Laser distance meter ep3c5e and stm32f407 50M
I work on a project "distance meter kit " Here is the link. http://asv-lab.ru/blog/fazovyj_lazer.../2015-06-26-12 There are videos. vide1<a href="https://youtu.be/lnKYCIw8I4E" target="_blank"...
View ArticleSignal distortion ADC/DAC on Cyclone III dev kit
Hi All, I'm new to FPGA's, and have been having difficulty doing basic signal I/O. I modified the factory example that came with the Cyclone III software (see attachment for block diagrams). This...
View Articleparallel adder package
I want to create a package which contain procedure for full adderprocedure for parallel adder using full adder defined in the same package but there is some error. Please check the source code...
View ArticleGetting started with Altera tools and FPGAs
hi, (altera beginner here!) im just getting started with Altera tools and FPGAs. could you point me to a document that gives me some basic information on the latest Altera tools, FPGAs, simulation...
View ArticleTerasic PCIe example designs unable to decrypt files
Hi all, I am trying to compile some reference designs (specifically PCIe_Fundamental and PCIe_ImageProcess) bundled with the Terasic DE5-Net. When I try to compile the projects, I first get an error...
View Articlejesd204b IP core have problem
When I use the altera_jesd204 IP core in my procedure ,I try to use modelsim-altera to do RTL simulations .Then I find this problem.When the modelsim compiles the altera_jesd204_8b10b_dec.v ,it find...
View ArticleConstraining interface with multiply clocks
Hi I got the following problem: FPGA is controlling DDS (AD9910) driver with internal clock sysclk running at 640 MHz. The spec says that dds control pins are sampled with sys_clk running 1/4 of sysclk...
View ArticleuCLinux, Quartus 15.0 and QSYS
Hello all, i began to use Quartus 15.0 and Qsys for design NIOS2 and other components system for MAX10 devices, but i need generate designs for Cyclone IV and file ptf for building uClinux image. Is...
View ArticleUFM MAX V problems on DEV KIT 5M570ZN
Hi, I'm attempting to use the altufm_parallel Megafunction. In that purpose, I used Qsys to configure my altufm_parallel block with 9 bits addr width, 16 bits word width and that it initialize itself...
View ArticleSTAP Mnemonic table problem
HEllo everybody, I don't know why even when i define a mnemonic table in order to match meaningfull strings with the decimal values taken by the state of a FSM , the result after choosing to display...
View ArticleEdit an existing custom Megafunction
Hi everybody, I am having a small problem. I am using the Altera Quartus Subscription edition 15. To interface with my DE4 board I wanted to use the Xillybus driver. Therefor I wanted to compile the...
View ArticleTCP/IP based remote signaltap on non-SoC device
Hello, Can I enable TCP/IP based remote signaltap on my device if I separately instantiate sld hub in the design? In my system there is a processor that talks to my device over an external bus. This...
View ArticlearriaII GX Transceiver (SDI)
I'm planning to use EP2AGX65.EP2AGX65 has 8 Transceiver channel(use for SDI). Channel names(pin name) are from GXB_x0x to GXB_x7x(X=p,n).Banks are QL0 and QL1 Refclk names(pin name) are...
View ArticleBit widths for addition
Hi, I am trying to write a pipelined adder for a filter design. all the gaussianPixels are 8 bits wide. gaussianPartialSum0 <= ("00" & gaussianPixels(0)) + ('0' & gaussianPixels(3) &...
View ArticleFFT MegaCore Usage
Hi all, I am working on a project including FFT transformation and I want to use the provided by Altera IP, but I am having some issues. As I see in the ReadMe file...
View ArticleRS232 rxd code
Hi :) i'm new here and i need some help... i work on project and i need to read from kind of machine some letters... there is an ascii code to all letter. this machine send words that i need to read...
View ArticleGenerating a pulse train at specific time on FPGA using VHDL programming.
Hello everyone. I am new to VHDL programming and FPGA. I would to generate a pulse train at specific time on FPGA using VHDL programming. The whole process is that 1. PC sent an array of specific time...
View ArticleFitter Critical Warning on "unable to find Transceiver Reconfiguration...
I am working on a project with stratix V development kit. I keep getting this critical warning message: Critical Warning (184043): Fitter was unable to find Transceiver Reconfiguration Controllers...
View ArticleIs it possible to convert a Web Edition install to Subscription install
I have the Quartus Web Edition installed, but I now have a valid subscription edition license. Can the web edition be converted/upgraded to the Subscription Edition or do I have to download and install...
View ArticleQuartus Test Bench not creating waveform in Modelsim
I have had an ongoing issue on my laptop for a class where when I try to launch Modelsim using a test bench written in Quartus, I have been having several issues. Originally, the program was unable to...
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