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Throughput Efficiency with half-rate DDR2 controller
I have been developed system which performs simultaneous writing and reading of the same DDR2 RAM (reading from the first half, writing to the second half). Read and write data (32 bit width) are...
View ArticleAFI Interface Timings for UniPHY
Hello! I am trying to use a custom controller to control the UniPHY interface in order to read and write to a DDR2 memory (to be synthesized on a DE3 board). The only timing information I've come...
View ArticleDisable EPCS ID check not available in Quartus 12.1
I am trying to use a M25PX16 as the AS configuration device for a Cyclone III as it allows the lower half of memory to be protected. I wanted to protect the FPGA image and be able to use the upper...
View Article12V instead of 9V PowerSupply for Nios Stratix Edition?
Hi, I've an old Nios DevKit (StratixEd, EP1S10). The UG says, I've to use a 9V PowerSupply, but due to the lack of 9V-Supply I want to know if it's possible to use a 12V Supply? On Board, there is an...
View ArticleHow to increase current strength on *_dq/dqs IOs of the UniPHY memory controller
Hi, UniPHY MegaWizard auto-generates current strength constraints for all IOs except *_dq and *_dqs. I need to figure out to increase current strength of those signals, because the voltage on our board...
View ArticleAvalon bridge accross fpgas using Dual Clock FIFOs and Alt-LVDS
Hi, I need a little advice/direction regarding connecting two fpgas via a bus. HW setup Stratix III (DE3) Stratix V 8 x LVDS Tx pairs ---------------------> 8 x LVDS Rx pairs Any other I/O...
View Articledaft question about Verilog parameter
Hi All, Is it legal to define a new parameter based on a previously declared one ? Thanks, Mark parameter HS64x8_XINC = 86; parameter HS64x8_X0POSN = 70; parameter HS64x8_X1POSN =...
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SOPC Erro upon Generate
Good day. I am trying to "re-create" a sample/demonstration project from University Program called D5M_Video_In using DE-2 DevKit. The sample uses the SOPC version 9.1 but i am using the later version,...
View ArticleQuartus is not inferring memory.
I'm using the verilog template for a single port rom. However, quartus is not inferring memory. I have any size ROM replacement on in alan&synth settings. What else could I be missing?
View Articlenios ii audio core help
hi, i am working on an audio project on DE2_115 board.I download the university program libraries for nios ii.I can not get the error message but my system doesn't work.:( please help me at SOPC builder.
View Articlede2_115 audio core
hi dear members, i make a simple project on DE2_115 board.It record sound and play it.But sound is very dirty.my c code is : #include <stdio.h> int i=0; #include "altera_up_avalon_audio.h" int...
View ArticleTimeQuest reporting paths between multiple LPM Divides
Hi, I'm using the latest version of Quartus (12.1 with sp1) and a number of LPM dividers in a Cyclone 3 FPGA design (plus other LPMs, RAMs, PLLs, VHDL modules, etc.,). The dividers in question all have...
View ArticleEmbedded MATLAB code in DSP Builder
Hi, I need to use some MATLAB functions that I have in .m files in a DSP Builder project. In a first example I tried to use an Embedded MATLAB function block with a simple and inside, but I have this...
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Best way to code a clock divider?
Hello, I have to divide a clock input signal by 2048. I was wondering which method was the best to implement this divider in a FPGA. I know that we can use either a counter or just some flip-flops...
View ArticleIssues with Quartus II web edition installation
Hello, I tried to install the quartus ii web edition (32 bit) and had been successful in installing that I hope. I downloaded the windows executable from the webpage:...
View ArticleAvalon data bus between two fpgas
Hi, I need a little advice/direction regarding connecting two fpgas via a bus. HW setup Stratix III (DE3) Stratix V 8 x LVDS Tx pairs ---------------------> 8 x LVDS Rx pairs Any other I/O...
View ArticleHow does RAM initialization *physically* work?
I understand how to initialize RAM from a .MIF with the Mega tool, I just don't understand how it works at a transistor level. Does the RAM have a property where it can initialize to a set value on...
View ArticleTSE TCP Stack problem
Hi, I have experienced a weird problem. The system is based on CycloneIII, TSE IP is connected to Marvell 88E6185 multiports switch (Port 9 as Phy). The system can send out UDP/IP and Ping. It can...
View Articleverilog sdram_dll module
Hi, I have to add an sdram_dll for my design, how can i have, or describe this module with verilog and thank you very much. cordally
View Articlehelp for vhdl processing image
Hi, I m new with vhdl, I have an image processing application to describe it with vhdl code, this application, is based on many mathematical function like, convolution, Gaussian filter, integration and...
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