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DSP Builder doesn't compile the Simulink files
Hello, thank you for see this post. DSP Builder doesn't compile the Simulink files. I'm using MATLAB R2013 Student Version. I want to transform my original Simulink file into VHDL file by...
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C to hardware acceleration
Hello Everyone I am doing hardware acceleration for edge detection( sobel). I have created custom component to transfer 8 values for sobel kernel and i will get result pixel value. Here I am attaching...
View ArticleVIP Suite Compatiblity between Cyclone III and IV GX (according to User Guide)
Hi everyone ! I am here today because I need someone to help me understand something about device compatibility with the VIP Suite (IP Core). So, for my project, I need to use the VIP Suite (Video and...
View ArticleCyclone V demo Code Compilation Error
Hi, I am using the cyclone GX V starter kit: http://www.terasic.com.tw/cgi-bin/pa...o=830&PartNo=1 I tried to configure my board with the ADC demo source code from this...
View ArticlePreloader issue with altera 13.0
hello I'm trying to build entire linux image(preloader, bootloader, kernel ...etc)for DE1-Soc board. first I thought I should understand the whole booting sequence, I planned to boot only preloader...
View Articleencrypt new generated qsys IP
Hello Everyone, Can we create enrypted Qsys custom IP? Can we encrypt newly generated Qsys IP HDL Synthesis files? Please help.. Thanks!
View ArticleSD/MMC controller and ACP possible?
Hello, I am trying to get the SD/MMC controller to work with the ACP ID mapper. Everything seems to work fine if I use uncached SDRAM or OCRAM for descriptors and buffers. But I can't get coherent...
View Articleaocl diagnostic failed for no reason
Hello everyone, I am doing a project using Nallatech P385-A72. When I type "aocl diagnostic" command, the result shows: Verified that the kernel mode driver is installed on the host machine. Using...
View ArticleVHDL Traffic Light - How to make signals viewable in simulation?
Hi there, relatively new to VHDL. At the end of this description I will post my VHDL code and Test Bench. When I simulate the code, the timing seems to be off, I want it to wait 15 clock cycles to go...
View ArticleWarning during simulation using modelsim 10.4b
Hi all, While running a design verification generated via qsys testbench, I'm continuously monitoring sink bfm for any new data/packet. During this, i get this warning. *** WARNING: vl_init_value,...
View ArticleBDF bus signal tap
Greetings, I have a block design which has some output pins defined, and it has an orthogonal node tool "wire" connected to a single output pin with a label "outpinXYZ." This signal has already been...
View ArticleAddressing unmapped memory space results in unpredictable behavior
Hi folks, Searching for a stubborn error, I came across the following behavior: When an avalon memory mapped master (for example NIOS) writes to an address, that is not mapped to any qsys component,...
View ArticleCyclone - and QuartusII 13
I found in the download file list at altera.com that Quartus II version 13.0 SP1 supports Cyclone (without II and higher as suffix) I still have a development board with a Cyclone and a JTAG interface,...
View ArticleProgrammatic Reset/Reconfig of Cyclone FPGA
Due to a funny situation, I need to programmatically trigger reboot/reconfiguration of my Cyclone IV E device. I mean that I need to reset/reconfigure the device from inside my VHDL code. Basically -...
View ArticleConfiguration of the SPI flash
Hi, I am trying to configure a Cyclone V FPGA using an external SPI flash (EPCQ256). I have a confusion in creating separate starting addresses for the default configuration and the upgrade...
View Articlemodelsim ase 10.4d/quartus lite 16.0,15.1 on linux source font problem
I can't read vhdl/verilog source because of too small font around 1pt. tools->edit preference->source windows->fixed font or text font size setting change was no effect. This problem is same...
View Articleall bins on tristate
Hello, Im working on a project with MAXV i got the pcb and soldered the cpld and it accept programming but all the pins give different voltages 0.9 1.7 2 v the Quartus 2 give successful build for they...
View ArticleSelecting Pages in a JIC file
Hi, I have created 3 pages in a jic file for reconfiguring the FPGA(Cyclone V) using the external SPI flash(EPCQ256). I wanted to know whether is there a method to select which page i want to use to...
View ArticleI have made a mistake in fpga design, in one bank vccpd is less than vccio ?
Arria V SX Soc, during my design, i made a mistake that the vccpd bank 8 is 2.5v, the vccio bank 8a and 8c 8d is 2.5v, however i set the vccio bank 8b is 3.3v:cry:..i forget the vccpd must great than...
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