Altera OpenCL SDK License issue
Hi, I recently got a license from Altera for a Stratix V machine. The board name is de5net_a7. I have set the following environment variables ALTERAOCLSDKROOT, LM_LICENSE_FILE, AOCL_BOARD_PACKAGE_ROOT...
View Articlewhat is DDIOOECELL?
Hello All, I have few queries ...... 1) What is DDIOOECELL? although i tried to look for an answer couldnt get one. 2) what code would interpret DDIOOECELL?
View ArticleFPGA-to-HPS SDRAM Bridge in Bare-metal
FPGA-to-HPS SDRAM Bridge in Bare-metal I am using DE1-SoC to start bare-metal programming for dual-core Cortex-A9 ARM hard processor, Cyclone V. I'm trying to read data from SDRAM to FPGA using...
View ArticleModelsim error with PLL if parameters for dynamic features is enabled
Quartus 16 patch 16.0.2.2.2.2 Modelsim 10.5d I've got error if checked Altera PLL -> Settings -> Enable access to dynamic phase shift portsor any other dynamic parameter The error is Code: #...
View ArticleHow to enable SDRAM ECC in the Qsys
Hi, How can I enable SDRAM ECC in the Qsys? Best Regards
View ArticleCyclone V SPI master releases chip select when TX FIFO runs empty. HOW TO...
Hi, I have noticed that the Cyclone V SPI master releases chip select when TX FIFO runs empty. I use Linux kernel 4.1, but the spi-dw driver is pretty much the same as in the latest kernel. The SPI...
View ArticleInterrupts using the ARM core and the GIC
I have been looking at the Altera documentation for the GIC on the Cyclone V device. Found here: ftp://ftp.altera.com/up/pub/Altera_M.../Using_GIC.pdf At the bottom of which (Appendix B) has some...
View ArticleNios Read Data Never Appears on Nios Read Bus
In our Arria 10 design, we have a custom IP block for the Nios data and instruction memory. The underlying memory consists of two 4Kx32 memory blocks, shared with other 64-bit processing elements in...
View ArticleHelp using ACP Port with EMAC on Cyclone V
I am trying to configure and use the Accelerator Coherency Port with EMAC1 on a Cyclone V. My understanding is that I should be able to place the descriptors and packet buffers in cachable, shared...
View ArticleQsys submodule entities unbound to top module
Hi, I found this problem trying to simulate in Questasim from a Qsys generated system. Specifically the 3-Wire SPI IP does not appear to bound to the top level .vhd file. The design will compile, but...
View ArticleLPM_MULT pipelining: changing input data while calculating
I am using the LPM_MULT megafunction to implement a 29 bit wide multiplier and setting the LPM_PIPELINE parameter to 2 for achieving the required speed to operate it at 100MHz. My understanding is that...
View ArticleBug report: Quartus will not load correct library in VHDL
Hello, I am a software-engineer and try to design circuits as a hobby. I had wanted to hide some modules/entities, such as C++'s namespace, or C's file-scope, so I have written designs in...
View ArticleAltera Cyclone V SoC FPGA Development Kit GPIO chip numbering
I am using an Altera Cyclone V SoC FPGA Development Kit, running a linux-socfpga-4.1.22-ltsi-rt kernel configured (DTB) using the socfpga_cyclone5_socdk.dtsi Within the (inherited) socfpga.dtsi I...
View ArticleQuartus reports:can't pass value from actual to argument xxx.
Consider the following code: Code: interface test_if #( parameter BITW = 16 ); logic [BITW-1:0] sigs; endinterface package test_pkg; function automatic int test_calc(int bitw);...
View Articleflash memory problem
Hi everyone, I'm a new user of FPGA and It seems I have some problem with flash memory In programmer, when I downloading the program sof in FPGA, I don't have any problem, but when I tried to...
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Altera Modelsim vsim-3601
Hi everyone! When i start simulation in quartus the following error message appear: "(vsim-3601) Iteration limit 5000 reached at time 0 ps" My testbench is: Code: `timescale 1 ns/ 1 nsmodule...
View ArticleOpenCores.org down for the last four days?
Anyone notice that OpenCores.org is down? It seems to be down for the last four days. Anyone that works with the site familiar if this is normal?
View ArticleStandard stdout through JTAG
I am interested in build the following environment through Nios II. Through a proper Qsys system, i.e., JTAG included, it is possible to use printf commands to be echoed in the Nios Console. Based on...
View ArticleAddition to MicroC OS/II
Hi all, I would like to ask you about MicroC OS/II. To illustrate, I would like to add a new service to the kernel of MicroC OS/II, and I want to verify if it works. Do you have any idea about this?...
View Articleuse DS-5 AE Evaluation for C code programming on DE0-NANO_SOC
Hi, I am trying to use DS-5 AE Evaluation for C code programming on DE0-NANO_SOC. when I load preloader the following message will be appeared: Stopping running target Altera - Cyclone V SoC (Dual...
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