Cyclone III development board SRAM revision D & E differences

Hi,

In the past I have been using Cyclone III development board revision D which was produced in 2007. We have a program that asynchronously accesses (write/read) to the external SRAM on Cyclone III development board. Everything was fine on all 5 boards we purchased earlier. This year, we purchased 3 more new cyclone III development board and this time the boards are revision E and we noticed the SRAM parts have been changed on revision E and the asynchronous access are also failing.

Symptoms:

Write 32 bits to address 0 of SRAM as an experiment, we notice regardless what you write to the SRAM, the outputs are always hex "00010001". Tried Altera's suggestions on memory M9K "https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05182010_977.html" Also slow down the write and read access does not help as well.

1) Does anyone have any suggestions?

2) Does anyone know where I can download the "Board Test System" so I can test the asynchronously read on the external SRAM. I followed the link https://www.altera.com/content/dam/a...iii_devkit.pdf, but what I found was just documents and sample tutorial codes.

Thanks for the help.