Mux for INOUT ports
Hey guys I'm trying to exchange 2 pairs of INOUT signals, but without much sucess so far. I have two PS/2 controlers and I would like to exchange the PS2(1) to PS2(2) signals and at same time PS2(2) to...
View Articleout_of_context mode equivalent in quartus tool
Hi Forum, I am a beginner in using quartus tool. I have a question regarding I/O buffer insertion in quartus. Earlier I used Vivado tool for synthesizing my design and I used out of context mode in...
View ArticleArria 10 SoC Development Kit - The function of FAHBP16 on Page 36
I am using Arria 10 SoC Development Kit (10AS066N3F40E2SG). And try to use the FMC A port for connecting an extra testing board. In the schematic (a10_soc_devkit_03_31_2016), some ports connect...
View ArticleHow to program EPCQ with .jic file on Altera C5EFP board?
I use C5EFP board, https://www.altera.com/products/boar...clone-v-e.html I program the EPCQ with jic file, get Error (209025): Can't recognize silicon ID for device 1 when it load 87%, but I can load...
View ArticleGenerated PCIe Gen3x8 example design for stratix 10 s1 board with "Enable DMA" ?
Hello all, In order to test and see the "HardIP for PCIe for stratix 10" IP component. I generated the example design from platform designer by configuring PCIe express IP with "Enable DMA option" and...
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LVDS Interface between two FPGA boards: Xilinx and Altera
Hi, I am making one-way communication between Cyclone V FPGA Board and Xilinx Kintex custom board. *Cyclone V FPGA Board: I/O standard = LVDS *Xilinx Kintex custom board: I/O standard =LVDS and LVDS_25...
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Xilinix to Quartus "Library Conversion"
Hi all, I have a library written by one of my ex-colleague for Xilinix ISE, It basically converts ML algorithms to HLS, Now I want to convert this library for Altera Fpga. I have used Altera...
View ArticleUnrolling and used RAMs
Hello, I'm trying to understand the relationship between channels, unrolls and used RAM (M20K) For this purpose, I've created this simple program composed of three kernels: - the first inject data into...
View Articlemem_fence() not working for channels
Hi all, I am testing the function of the feed-forward model(ping-pong buffer) mentioned in the programming guide. And I found the mem_fence function is not working. Here's the code I used for testing:...
View Articleconnect FPFA TO Internet using wifi adapter
I need help please ,How can I connect my board DE1-Soc FPGA to internet I have Wifi adapter RT5370 Wireless Adapter
View Articleresetn for all HDL module ?
Hi, I have HDL module (is a counter) implemented with OpenCL kernel (like example 1 in Intel examples). This HDL module is called many times in the same kernel. As I understand each call of HDL module...
View ArticleHow to guarantee the maximum frequency when combine multiple IP cores?
Im planning to design a signal processing system with Arria 10 SOC, using ALTERA_FP_FUNCTIONS, on-chip RAM and FFT IP Core. Each of IP Core works correctly with the frequency up to 350MHz, but the...
View ArticleHow to make a FLAG using verilog
Dear Community, Ive two modules on is parsing the USART RX signal and the other one is a state machine which shall do something else in case the first module founds e.g. the word read inside the...
View ArticleIf loop with parameters.
I have this bothering me for quite some time now. I make a simple loop with ifs to create a state machine, where I just want stuff to happen in a certain order after some flags are activated. Something...
View ArticleNetwork Manager problem
Hello, please I need help , I Follow this tutorial ftp://ftp.intel.com/Pub/fpgaup/pub/I...ies_Boards.pdf I downloaded the linux distrubtion I try to connect my board to the Internet using Wifi adapter...
View ArticleCyclone V SoC RSDS speed
I'm beginning an application that requires RSDS output, and am finding information that leads to ambiguous conclusions. RSDS is specifically mentioned in the Cyclone V High-Speed I/O Specifications;...
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Mysterious trouble sharing FPGA RAM with HPS
Hello all I'm a hobbyist and I'm trying to learn verilog and FPGA design by building a PDP-8 simulator. I've built the verilog for the PDP8 and it passes all the test code when run on a simulator. I'm...
View ArticleWhich Linux distributions work best with Quartus software?
I've bought a device that is based on the DE-0 Nano. The maker puts out new versions of the firmware to fix bugs or make improvements, so I need only install them, and hence should just need the...
View ArticleProblem in accessing Quartus floating license using VPN
Hi, A quartus floating license is installed on a server in a US university. When I was in the US, I was able to access the quartus license from outside the university using VPN (Cisco AnyConnect), but...
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MAX10 Development Kit Board name, P/N and version corrupt
After successfully having set up Linux on the MAX10 Dev Kit (using the tutorial from rocketboards for rev. C kit) and factory restoring (using the design examples included with the kit), the board...
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