LE vs LUT vs Logic Gate. What is the relatioship/distinction between them?
I understand that the answer to this question may become quite lengthy. Thus my question is, where can I find the clear distinction made between Logic element, Look up table and Logic gate on FPGAs?
View Articlewhy the results i run or debug this code are different,your help would be...
/* * control.c * * Created on: 2012-11-15 * Author: zhanghan */ #include "alt_types.h" #include "altera_avalon_timer_regs.h" #include "sys/alt_irq.h" #include "system.h" #include <stdio.h>...
View Articleplease help me about avering of array at 1 clc pulse
hello, I'm trying to making avering filter.First ı create a matrix which is 4*4.And I covered this vith zeros to protect size of matrix. and after that I make filtering process. then I save the values...
View ArticleBlock Floating Point
I was wondering if anyone has implemented 'Block Floating Point' arithmetic in their FPGA designs? I understand the the Altera FFT Core uses it, but there is no supporting documentation that I have...
View ArticleWhat are the control and data planes in Altera Qsys?
What are Control and data planes, and why do we need them in the first place?
View ArticleDownloading data directly to FPGA (not FPGA configuration)
I'm doing some heavy algorithm stuff in a Stratix IV eval kit. I need to download large amounts of test data to external memory (SDRAM, SRAM, etc.) from windows, process the data in the FPGA, retrieve...
View ArticleWhat is a BFM in Qsys and why should we need one
As far as I understand it, the BFM is used for simulation purpose and it is an acronym for Bus Functional Model. What I do not understand is that, why should we need one of these. Can't we just do...
View ArticleAvalon-ST interface with the TSE -> how to detect the interrupted transmission
Hi All, I'm designing the Custom IP that communicates directly with the TSE Core via the Avalon-ST interface. I couldn't find information *how to detect* that the transmission has been suddenly broken...
View Articleproblem with VGA display of a static image
Hello ALL please i've a question concerning the display of an image on VGA using FPGA i have the DE2 Board with cyclone II FPGA chip i created a quartus project,i've a VGA Controller that is working...
View ArticleSOF file
Where do I find the location of the final output programming file (e.g. sof file) after a I have performed a full compilation? How do I set its location and type? Thank you.
View ArticleAudio Codec
Hi all, I have a question regarding the audio codec inside the DE2 board. I'm trying to DE2 board audio codec as my AD/DA convertor for audio signals. Apparently, altera has this as lab 12 in the...
View ArticleVHDL Loop Statement error...loop must terminate within 10,000 iterations
I have this module of source code: procedure init_mem_data (signal mem : out mem_ty)is variable buf : line; file infile : text ; -- s in "data.txt" ; variable word : std_logic_vector(7 downto 0);...
View ArticleCyclone V GX evaluation kit question
Hi, I want to use the Cyclone V GX PCIe evaluation kit (http://www.altera.com/products/devki...lone-v-gx.html). I need to design a daughter board that will connect to the FPGA via the HSMC connector...
View Articleqsys port export and internal wiring
Hello! I´ve got a question regarding qsys system. Is it possible to use a port of an IP block for internal wiring to another IP block and for export to my top sheet (as it was in SOPC). e.g.: i´ve...
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How to infer systolic FIR mode DSP block in Arria V
Hi, Do someone know good ways to infer systolic FIR mode DSP block in Arria V? I develop the code attached, but it doesn't fit into one DSP block. I need the block to implement complex FIR filter....
View Articleinstallation problem
hello everybody I have a problem on installation quartus 12.1 web edition I downloaded it successfully but when I try to install its stuck on 6% and I don't know what to do I try to run on win xp...
View ArticleGenerating a signal with noise
What i am doing is i am trying to do is add random numbers to a signal to find PSD later. I wrote a code for random numbers generator which is working fine shown below: LIBRARY ieee; USE...
View ArticleCyclone IV PLL lock range: datasheet vs measurement
Hi, According to the Cyclone IV device datasheet, the: - PFD frequency (Fin/N) should range from 5MHz to 325MHz; - VCO frequency (Fin*M/N) should range from 600MHz to 1300MHz. When I measure these min...
View ArticleIs it possible that different paths in a pipelined architecure have differnet...
If we have 2 pipelines connecting the same stage at the end, it is possible that the two end up having different latency. In this case the stage they both connect to will have to wait for one of them...
View ArticleTCP/IP communication using DE2
Hi, i need some ideas to be able to start with my project. My project is to capture image using a camera and transfer to FPGA. FPGA will be connected to the LAN port of router. My question is how do i...
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