DDR3 variation file generation on Q10.1
Hi BACKGROUND: I'm trying to compile a project to run on the Arria II GX development kit. the project includes an SOPC system with Nios DMAs and RAM. since the SRAM is too small I need to use the DDR3...
View ArticleMessage suppression file (*.srf) is not recognized by quartus
Hi! I want to use an default *.srf to disable some warnings. The project is autogenerated by a tcl script. To autogenerate the message suppressions, I just copy an *.srf file into the project dir and...
View Articlethe simulation and animated signals in Quatrus
hello all i wanted to ask if its possible to do the simulation in Quantus 2 that can show you the flew signal through the logical gates i mean tracking the signals , (not like in the wave form just see...
View ArticleDDR3 -> SGDMA -> TSE throughput
I've got a Qsys system where I'm buffering up data into a DDR3 and then DMAing it to the TX port on my Triple Speed Ethernet. The DDR3 is running at 333Mhz. The rest of the Avalon components including...
View ArticleNios Trace Format
is there a documentation for the Nios trace format? The handbook says it's in a compressed format, I'd like to know the format if it's not super secret information.
View Articlesof v12.1
can I convert SOF file from the version of the Quartus II 12.1 in the format of the Quartus II 12.0?
View ArticleAddition of a vector with a integer in vhdl code
There is a vector A(7 down to 0).Now we have to add this vector with an integer(let it be 5).B(7 down to 0) is output.Then how to write the vhdl code.
View Articlesof v12.1 to v11.1
Can I convert SOF file from the version of the Quartus II 12.1 in the format of the Quartus II 11.1? The problem is that SOF file from version 12.1 no programs the Quartus Programmer 11.1. I need to...
View ArticleLearning timequest timing analysis
I am trying to learn how the TimeQuest timing analyzer is used. It would benefit me greatly if I can have access to some labs that make a person go step by step through assigning constraints and fixing...
View ArticleI want to use clock oscillator...
Hi. I have DE0 board and it has 50MHz clock oscillator. I want to make a digital clock, and I know How to change 50MHZ to 1Hz, But I don't know how to make the 50MHz oscillator start. When i push the...
View ArticleHDL error when making digital clock
error : cant' infer register for "rst_n" because its behavior does not match any supported register model. error : cant' infer register for "hour_2p[x],hour_count[x],minute_2p[x],minut_count[x]"...
View ArticleWarning (18029): Output pin [...] cannot be tri-stated
Hi, I get the following warning (for each line of "Data") in my design: "Warning (18029): Output pin "_subnet_pin_406" driven by bidirectional pin "Data(0)" cannot be tri-stated" "Data" is a...
View ArticleWhat are "worst case path" and "critical path", how are they similar or...
Critical path is the path that takes the longest duration to complete in the circuit, it is between 2 registers. Making the clock cycle any smaller may result in this being failed and thus it is called...
View ArticleCyclone IV GX Transceiver Starter Kit nterface with ADC module
I wonder who has done a project that interface the Cyclone IV GX transceiver starter kit with an ADC module. I need an ADC module having sampling frequency up to at least 20Mhz. What should I consider...
View ArticleJTAG UART hangs on disconnection of terminal
Dear all, is there any reason why JTAG should hang? I periodically send from my NIOS application debugging data over JTAG UART to my pc. If nios-terminal is running, everything works pretty nicely. If...
View Articleproblem connecting DE1 board to computer
Starting with Quartus II program to the point of connecting to DE1 board. After choosing from toolbar "Tools>Programmer" with the "Programmer" window, the space next to the icon"Hardware Setup"...
View ArticleGenlock - master source (DVI) + one framebuffered camera source
Hi, I'm trying to build a system that can overlay a camerasignal to a DVI signal from my PC . (using Altera VIP) Here ist my setup so far:...
View ArticleStratix III Development Kit Embedded USB Blaster Problem
Hi everyone, I use Stratix III 3SL150 Development Board. However, I have encountered with a JTAG problem when using the Embedded USB Blaster. At the beginning everything was ok, I was able to program...
View ArticleLow Pass Frequency Filter in Verilog
Hello, I am trying to implement a low pass frequency filter in Verilog. I know that the input is a sine wave that oscilates around 0. The threshold is 500hz. Here is my code: module filter(clk, in,...
View ArticleCyclone III FPGA Starter Kit
Can anyone tell me the specs of the standard external power supply that come with the Cyclone III FPGA Starter Kit?
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