Low Pass Frequency Filter in Verilog

Hello,
I am trying to implement a low pass frequency filter in Verilog. I know that the input is a sine wave that oscilates around 0. The threshold is 500hz. Here is my code:
module filter(clk, in, out);
input signed [11:0]in;
output signed [13:0]out;
input clk;
reg [17:0]counter;
wire [13:0]out;
reg q;
reg [11:0]true;
reg s;
initial begin counter=18'b000000000000000000; q=1; true=12'b000000000000; s=1; end
always @(posedge clk) begin
if(counter[17]==0) counter=counter+1;
if(~q==s) begin s=q; counter=18'b00000000000000; end
end
always @(negedge in[11]) begin
true={counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17],counter[17]};
q=~q;
end
assign out=(in & true)<<< 2;
endmodule

The output is just 0 for no matter what frequency of the input.(The input is converted in a 2's complement system)
Will be very happy to hear how to fix my program... but if it desperately stupid, would like to see a code for LPFF.
Thanks in advance