HDL error when making digital clock

error : cant' infer register for "rst_n" because its behavior does not match any supported register model.
error : cant' infer register for "hour_2p[x],hour_count[x],minute_2p[x],minut_count[x]" because its behavior does not match any supported register model.
error :

first code is error code. second one is working well.
when I changed red letter in first code to blue letter in second code, errors are removed. ( both code are all the same except color letter.)
but I have to use red letter( I have to use that rising edge trigger!!).
How can I solve the problem?


first code
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter_time is
port(
hour_2p : out std_logic_vector(5 downto 0);
minute_2p : out std_logic_vector(5 downto 0);
second_2p : out std_logic_vector(5 downto 0);
second_edge, minute_edge, hour_edge : buffer std_logic;
rst_n : buffer std_logic;
clk : in std_Logic);
end counter_time;
ARCHITECTURE arc of counter_time is
signal clock_count : std_logic_vector(3 downto 0);
signal second_pulse : std_logic;
signal minute_pulse : std_logic;
signal hour_pulse : std_logic;
signal second_count : std_Logic_vector(5 downto 0);
signal minute_count : std_logic_vector(5 downto 0);
signal hour_count : std_logic_vector(5 downto 0);
constant clock_cnt : integer := 9;
constant second_cnt : integer := 59;
constant minute_cnt : integer := 59;
constant hour_cnt : integer := 23;


begin
process(rst_n,clk)
begin
if(rst_n ='0') then
clock_count <= (others =>'0');
second_pulse <= '0';
elsif(clk'event and clk ='1') then
if clock_count < clock_cnt then
clock_count<= clock_count + 1;
else
clock_count<= (others => '0');
end if;
if clock_count = clock_cnt then
second_pulse <='1';
else
second_pulse <= '0';
end if;
second_edge<= second_pulse;
end if;
end process;
process(rst_n,clk)
begin
if(rst_n ='0') then
second_count <= (others => '0');
minute_pulse <= '0';
second_2p <= (others => '0');
elsif(clk'event and clk = '1') then
if (second_edge'event and second_edge = '1') then
if second_count < second_cnt then
second_count <= second_count + 1;
else
second_count <= (others => '0');
end if;
second_2p<= second_count;

if second_count = second_cnt then
minute_pulse <= '1';
else
minute_pulse <='0';
end if;
minute_edge<=minute_pulse;
end if;
end if;
end process;
process(rst_n,clk)
begin
if(rst_n ='0') then
minute_count <= (others => '0');
hour_pulse <= '0';
minute_2p <= (others => '0');
elsif(clk'event and clk = '1') then
if (minute_edge'event and minute_edge = '1') then
if minute_count < minute_cnt then
minute_count <= minute_count + 1;
else
minute_count <= (others => '0');
end if;
minute_2p<= minute_count;

if minute_count = minute_cnt then
hour_pulse <= '1';
else
hour_pulse <='0';
end if;
hour_edge<=hour_pulse;
end if;
end if;
end process;
process(rst_n,clk)
begin
if(rst_n ='0') then
hour_count <= (others => '0');
hour_2p <= (others => '0');
elsif(clk'event and clk = '1') then
if (hour_edge'event and hour_edge = '1') then
if hour_count < hour_cnt then
hour_count <= hour_count + 1;
else
hour_count <= (others => '0');
end if;
hour_2p<= hour_count;

if hour_count = hour_cnt then
rst_n<= '0';
end if;
end if;
end if;
end process;
end arc;
------------------------------------------
-------------------------------------------


second code

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter_time is
port(
hour_2p : out std_logic_vector(5 downto 0);
minute_2p : out std_logic_vector(5 downto 0);
second_2p : out std_logic_vector(5 downto 0);
second_edge, minute_edge, hour_edge : buffer std_logic;
rst_n : buffer std_logic;
clk : in std_Logic);
end counter_time;
ARCHITECTURE arc of counter_time is
signal clock_count : std_logic_vector(3 downto 0);
signal second_pulse : std_logic;
signal minute_pulse : std_logic;
signal hour_pulse : std_logic;
signal second_count : std_Logic_vector(5 downto 0);
signal minute_count : std_logic_vector(5 downto 0);
signal hour_count : std_logic_vector(5 downto 0);
constant clock_cnt : integer := 9;
constant second_cnt : integer := 59;
constant minute_cnt : integer := 59;
constant hour_cnt : integer := 23;


begin
process(rst_n,clk)
begin
if(rst_n ='0') then
clock_count <= (others =>'0');
second_pulse <= '0';
elsif(clk'event and clk ='1') then
if clock_count < clock_cnt then
clock_count<= clock_count + 1;
else
clock_count<= (others => '0');
end if;
if clock_count = clock_cnt then
second_pulse <='1';
else
second_pulse <= '0';
end if;
second_edge<= second_pulse;
end if;
end process;
process(rst_n,clk)
begin
if(rst_n ='0') then
second_count <= (others => '0');
minute_pulse <= '0';
second_2p <= (others => '0');
elsif(clk'event and clk = '1') then
if (second_edge = '1') then
if second_count < second_cnt then
second_count <= second_count + 1;
else
second_count <= (others => '0');
end if;
second_2p<= second_count;

if second_count = second_cnt then
minute_pulse <= '1';
else
minute_pulse <='0';
end if;
minute_edge<=minute_pulse;
end if;
end if;
end process;
process(rst_n,clk)
begin
if(rst_n ='0') then
minute_count <= (others => '0');
hour_pulse <= '0';
minute_2p <= (others => '0');
elsif(clk'event and clk = '1') then
if (minute_edge = '1') then
if minute_count < minute_cnt then
minute_count <= minute_count + 1;
else
minute_count <= (others => '0');
end if;
minute_2p<= minute_count;

if minute_count = minute_cnt then
hour_pulse <= '1';
else
hour_pulse <='0';
end if;
hour_edge<=hour_pulse;
end if;
end if;
end process;
process(rst_n,clk)
begin
if(rst_n ='0') then
hour_count <= (others => '0');
hour_2p <= (others => '0');
elsif(clk'event and clk = '1') then
if (hour_edge = '1') then
if hour_count < hour_cnt then
hour_count <= hour_count + 1;
else
hour_count <= (others => '0');
end if;
hour_2p<= hour_count;

if hour_count = hour_cnt then
rst_n<= '0';
end if;
end if;
end if;
end process;
end arc;