Hello,
I'm working with Quartus II, and had implemented the Triple-Speed Ethernet Megacore.
I simulate my design with ModelSim Altera Starter Edition.
My hardware is the BeMicro CV A9 with a Cyclone V FPGA and a Micrel Phy (KSZ9021RN).
I set the signals ff_tx_data, ff_tx_sop, ff_tx_eop and ff_tx_wren (from my PaketGenerator). And in my simulation, I got some signals on rgmii_out and tx_control (tx_control seems to be strange, isn't it?) Of course there is a 100-MHz-signal for ff_tx_clk and a 25-MHz-signal for tx_clk (I want to transmit at 100 MBit/s).
Is the simulation right?
And why my FPGA board doesn't work in reality and doesn't transmit any frames? (in the statistic counters of the TSE I got sometimes in register 0x1A one paket (but on my host I don't receive any paket), mostly I got in register 0x23 one paket - I send 10000 pakets in reallity and 10 pakets in simulation)
Look also at the photos I added to this request.
Kind regards, Matthias
I'm working with Quartus II, and had implemented the Triple-Speed Ethernet Megacore.
I simulate my design with ModelSim Altera Starter Edition.
My hardware is the BeMicro CV A9 with a Cyclone V FPGA and a Micrel Phy (KSZ9021RN).
I set the signals ff_tx_data, ff_tx_sop, ff_tx_eop and ff_tx_wren (from my PaketGenerator). And in my simulation, I got some signals on rgmii_out and tx_control (tx_control seems to be strange, isn't it?) Of course there is a 100-MHz-signal for ff_tx_clk and a 25-MHz-signal for tx_clk (I want to transmit at 100 MBit/s).
Is the simulation right?
And why my FPGA board doesn't work in reality and doesn't transmit any frames? (in the statistic counters of the TSE I got sometimes in register 0x1A one paket (but on my host I don't receive any paket), mostly I got in register 0x23 one paket - I send 10000 pakets in reallity and 10 pakets in simulation)
Look also at the photos I added to this request.
Kind regards, Matthias