LVDS Differential Clock input to single-ended output

How can I convert an LVDS Clock input to the Cyclone IV GX to a single-ended output? I basically have a 125 MHz differential clock input and want to pass it as a single-ended clock source to another FPGA (MAX10) for synchronization purposes. I believe in Xilinx, I would use the IBUFGDS design element. What's the Altera counterpart? The library that IBUFGDS references to (UNISIM) is proprietary to Xilinx if I'm not mistaken. Is the ALTIOBUF IP Core similar to this?

Another question is that how can I connect/reference the negative pin into the design as the top level only declares one port as shown in picture 1 but on pin planner it's connected as two pins as shown in picture 2.


Regards,

Attached Images

• 1.JPG (19.5 KB)
• 2.JPG (23.2 KB)