Generate VHDL code from VHDL code

Hello,
I have been wondering for a while if it is possible to let some standard tool (like quartus, or ISE or maybe even a windows tool) generate a VHDL file from previous written VHDL code.
For example when you have some different VHDL files you have written before, and theyre all reusable. Is it possible to say; I want these 3 files working together and now try and make a toplevel for me?
Or do you have to write your own file in a different language that links them all together?

I hope it is somewhat clear, but I can understand that it might be too vague, so please ask questions that might help making my question clear.

Thanks in advance