Hi All,
I'm receiving the "Error (10928): SystemVerilog error at rly.v(141): enum type cannot be assigned to enum type - enum target requires cast" while compiling my code.
Here is the code:
So, what's the problem? How to fix?
Dmitry
I'm receiving the "Error (10928): SystemVerilog error at rly.v(141): enum type cannot be assigned to enum type - enum target requires cast" while compiling my code.
Here is the code:
Code:
typedef enum reg [31:0] {
IDLE,
LOAD,
SHIFT}
rly_fsm_t;
rly_fsm_t state, nxt_state;
rly_fsm #(/*AUTOINSTPARAM*/
// Parameters
.L (DW)) // Templated
i_rly_fsm (//***
/*AUTOINST*/
// Interfaces
.state (state),
.nxt_state (nxt_state),
// Inputs
.clk (clk),
.rstn (rstn),
.go (cmd_rdy));Dmitry