I wrote a verilog program as follow
UD_Cnt(CLK,UD_counter) is a Up-down counter module,
CPS_PWM(CLK,Cx) is a PWM module, containing multiple UD_Cnt module with different initial value。
UD_cnt is invoked in main module(CPLD5) and CPS_PWM.
I used quartus II 15.1 to compile this project, then simulated in quartus. The simulate result shows that, only the UD_cnt of UDxx in CP1 is correct. The initial value of UDxx in CPLD5 and UD2 UD3 UD4 in CP1 in wrong. It seems that, only the counter which is finally output in CPLD5 is correct.
Then I used modelsim to simulate the same project, and everything is fine, the initial value of every counter is correct.
Did anyone knows what's wrong with my project?
UD_Cnt(CLK,UD_counter) is a Up-down counter module,
CPS_PWM(CLK,Cx) is a PWM module, containing multiple UD_Cnt module with different initial value。
UD_cnt is invoked in main module(CPLD5) and CPS_PWM.
I used quartus II 15.1 to compile this project, then simulated in quartus. The simulate result shows that, only the UD_cnt of UDxx in CP1 is correct. The initial value of UDxx in CPLD5 and UD2 UD3 UD4 in CP1 in wrong. It seems that, only the counter which is finally output in CPLD5 is correct.
Then I used modelsim to simulate the same project, and everything is fine, the initial value of every counter is correct.
Did anyone knows what's wrong with my project?
Code:
moduleCPLD5(CLK_150M,CS,RD,XA,XD,Aup,Adown,Bup,Bdown,Cup,Cdown,UD_counter,O1,O2,O3,o4,CLK1M,Cx);/*synthesis noprune*/ parameter cntini = 511;
input CLK_150M,CS,RD;
input[4:0] XA;
input[15:0] XD;
output[7:0] Aup,Adown,Bup,Bdown,Cup,Cdown;
output[10:0] UD_counter,Cx;
wire[10:0] CC;
output O1,O2,O3,o4;
output CLK1M;
UD_Cnt #(257) UDxx(CLK_150M,CC);
CPS_PWM CP1(CLK_150M,UD_counter);
endmodule
module CPS_PWM(CLK,Cx);/*synthesis noprune*/
input CLK;
output[10:0] Cx;
wire[10:0] C1,C2,C3;/*synthesis noprune*/
UD_Cnt #(259) UDxx(CLK,Cx);
UD_Cnt #(0,0) UD2(CLK,C1);
UD_Cnt #((500/2),1) UD3(CLK,C2);
UD_Cnt #(500,0) UD4(CLK,C3);
endmodule
module UD_Cnt(CLK,UD_counter);/*synthesis noprune*/
parameter CNT_ini = 167,Dir_ini = 0;
input CLK;
output reg[10:0] UD_counter;
reg Dir;
initial
begin
UD_counter = CNT_ini;
Dir = Dir_ini;
end
always@ (posedge CLK)
begin
if(Dir == 0)
UD_counter = UD_counter + 1;
else
UD_counter = UD_counter - 1;
end
always@ (posedge CLK)
begin
if((UD_counter == 500)&(Dir == 0))
Dir = 1;
else if((UD_counter == 1)&(Dir == 1))
Dir = 0;
end
endmodule