why i cannot creat my control part properly

as mmTsuchi sir suggestion i m posting my code again....plz see the problem in modelsim simulator....becoz problem is like i cannot discribe
....i am taking refernce from dougles l perry.... and addressis immediate data type....plz co-opreate if i mistake about the posting i m new in this site
[library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package cpu_lib is
type t_shift is (shiftpass, shl, shr, rotl, rotr);
subtype t_alu is unsigned(4 downto 0);
constant alupass : unsigned(4 downto 0) := "00000";
constant andOp : unsigned(4 downto 0) := "00001";
constant orOp : unsigned(4 downto 0) := "00100";
constant notOp : unsigned(4 downto 0) := "00110";
constant xorOp : unsigned(4 downto 0) := "01000";
constant plus : unsigned(4 downto 0) := "01010";
constant alusub : unsigned(4 downto 0) := "01100";
constant inc : unsigned(4 downto 0) := "01110";
constant dec : unsigned(4 downto 0) := "10000";
constant zero : unsigned(4 downto 0) := "10010";
subtype t_reg is std_logic_vector(2 downto 0);
type state is (reset1, reset2, reset3, reset4, reset5, execute,
nop, load, andop1, load2, load3, load4,andop2,andop3, incPc,
incPc2, incPc3, incPc4,incpc5,incpc6);
subtype bit16 is std_logic_vector(15 downto 0);
subtype bit8 is std_logic_vector(7 downto 0);
end cpu_lib;

library IEEE;
use IEEE.std_logic_1164.all;
use work.cpu_lib.all;
entity cpu is
port(clock, reset, ready : in std_logic;
addr_in : in bit16;
data_out : out bit8);
end cpu;
architecture rtl of cpu is
component regarray
port( data : in bit8;
sel : in t_reg;
en : in std_logic;
clk : in std_logic;
q : out bit8);
end component;

component trireg1
port( a : in bit16;
en : in std_logic;
clk : in std_logic;
q : out bit16);
end component;
component trireg2
port(a:in bit8;
en:in std_logic;
clk:in std_logic;
q:out bit8);
end component;

component reg
port( a : in bit16;
clk : in std_logic;
q : out bit8);
end component;

component control
port( addr_in: in bit16;
clock : in std_logic;
ready : in std_logic;
reset : in std_logic;
instrwr:out std_logic;
opRegwr : out std_logic;
opRegrd : out std_logic;
outRegWr : out std_logic;
outRegRd : out std_logic;
regwr : out std_logic;
regrd : out std_logic;
shiftSel : out t_shift;
aluSel : out t_alu;
regSel : out t_reg

);
end component;
component alu
port( a, b : in bit8;
sel : in t_alu;
c : out bit8);
end component;
component shift
port ( a : in bit8;
sel : in t_shift;
y : out bit8);
end component;
signal data: bit8;
signal opdata, aluout, shiftout : bit8;
signal regsel : t_reg;
signal regRd, regWr, opregRd, opregWr, outregRd, outregWr,instrWr : std_logic;
signal alusel : t_alu;
signal shiftsel : t_shift;


begin
ra1 : regarray port map(data, regsel, regRd, regWr, data);
opreg: trireg2 port map (data, opregRd, opregWr, opdata);
alu1: alu port map (data, opdata, alusel, aluout);
shift1: shift port map (aluout, shiftsel, shiftout);
outreg: trireg2 port map (shiftout, outregRd, outregWr, data_out);
instr1: reg port map (addr_in, instrwr, data);
con: control port map ( addr_in, clock, reset, ready, outregWr, outregRd, shiftsel, alusel,
opregRd, opregWr, regsel, regRd, regWr, instrwr);


end rtl;

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.cpu_lib.all;
entity alu is
port( a, b : in bit8;
sel : in t_alu;
c : out bit8);
end alu;
architecture rtl of alu is
begin
aluproc: process(a, b, sel)
begin
case sel is
when alupass =>
c <= a ;
when andOp =>
c <= a and b;
when orOp =>
c <= a or b ;
when xorOp =>
c <= a xor b;
when notOp =>
c <= not a;
when plus =>
c <= a + b;
when alusub =>
c <= a - b;
when inc =>
c <= a + "00000001";
when dec =>
c <= a - "00000001";
when others =>
c <= "00000000";
end case;
end process;
end rtl;

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.cpu_lib.all;
entity regarray is
port( data : in bit8;
sel : in t_reg;
en : in std_logic;
clk : in std_logic;
q : out bit8);
end regarray;
architecture rtl of regarray is
type t_ram is array (0 to 7) of bit8;
signal temp_data : bit8;
begin
process(clk,sel)
variable ramdata : t_ram;
begin
if clk'event and clk = '1' then
ramdata(conv_integer(sel)) := data;
end if;
temp_data <= ramdata(conv_integer(sel));
end process;
process(en, temp_data)
begin
if en = '1' then
q <= temp_data;
else
q <= "ZZZZZZZZ";
end if;
end process;
end rtl;

library IEEE;
use IEEE.std_logic_1164.all;
use work.cpu_lib.all;
entity shift is
port ( a : in bit8;
sel : in t_shift;
y : out bit8);
end shift;
architecture rtl of shift is
begin
shftproc: process(a, sel)
begin
case sel is
when shiftpass =>
y <= a ;
when shl =>
y <= a(6 downto 0) & '0' ;
when shr =>
y <= '0' & a(7 downto 1);
when rotl =>
y <= a(6 downto 0) & a(7);
when rotr =>
y <= a(0) & a(7 downto 1);
end case;
end process;
end rtl;

library IEEE;
use IEEE.std_logic_1164.all;
use work.cpu_lib.all;
entity trireg2 is
port( a : in bit8;
en : in std_logic;
clk : in std_logic;
q : out bit8);
end trireg2;
architecture rtl of trireg2 is
signal val :bit8;
begin
triregdata: process
begin
wait until clk'event and clk = '1';
val <= a;
end process;
trireg3st: process(en, val)
begin
if en = '1' then
q <= val ;
elsif en = '0' then
q <= "ZZZZZZZZ";
else
q <= "XXXXXXXX";
end if;
end process;
end rtl;

library ieee;
use ieee.std_logic_1164.all;
use work.cpu_lib.all;
entity reg is
port(a:in bit16;
clk:in std_logic;
q:out bit8);
end reg;
architecture rtl of reg is
begin
regproc:process
begin
wait until clk'event and clk='1';
q<=a(10 downto 3);
end process;
end rtl;

library IEEE;
use IEEE.std_logic_1164.all;
use work.cpu_lib.all;
entity control is
port( clock : in std_logic;
reset : in std_logic;
addr_in : in bit16;
ready : in std_logic;
outRegWr : out std_logic;
outRegRd : out std_logic;
shiftSel : out t_shift;
aluSel : out t_alu;
opRegRd : out std_logic;
opRegWr : out std_logic;
instrWr : out std_logic;
regSel : out t_reg;
regRd : out std_logic;
regWr : out std_logic
);
end control;
architecture rtl of control is
signal current_state, next_state : state;
begin
nxtstateproc: process( current_state,next_state,addr_in)
begin
outRegWr <= '0';
outRegRd <= '0';
shiftSel <= shiftpass;
aluSel <= alupass;
opRegRd <= '0';
opRegWr <= '0';
instrWr <= '0';
regSel <= "000";
regRd <= '0';
regWr <= '0';

case current_state is
when reset1 =>
aluSel <= alupass;
shiftSel <= shiftpass;
next_state <= reset2;
when reset2 =>
aluSel <= alupass;
shiftSel <= shiftpass;
outRegWr <= '1';
next_state <= reset3;
when reset3 =>
outRegRd <= '1';

next_state <= reset4;
when reset4 =>
if ready = '1' then
instrWr <= '1';
next_state <= execute;
else
next_state <= reset5;
end if;
when execute =>
case addr_in(15 downto 11) is
when "00000" =>
next_state <= incPc;
when "00001" =>
regSel <= addr_in(2 downto 0);
regRd <= '1';
next_state <= load2;

when "00010" => --- andop
regSel <= addr_in(2 downto 0);
regRd <= '1';
next_state <= andop1;

when others =>
next_state <= incPc;
end case;
when load2 =>
regSel <= addr_in(2 downto 0);
regRd <= '1';
next_state <= load3;
when load3 =>
regSel <= addr_in(2 downto 0);
regWr <= '1';

next_state <= incPc;
when andop1 =>
regSel <= addr_in(2 downto 0);
regRd <= '1';
opregwr<='1';
next_state <= andop2;
when andop2 =>
alusel<= andop;
shiftsel <= shiftpass;
outregwr<='1';
next_state <= andop3;
when andop3 =>
outregrd<='1';
next_state <= incPc;
when incPc =>

alusel <= alupass;
shiftsel <= shiftpass;
next_state <= incPc2;
when incPc2 =>

alusel <= alupass;
shiftsel <= shiftpass;
outregWr <= '1';
next_state <= incPc3;
when incPc3 =>
outregRd <= '1';
next_state <= incPc4;

when incPc4 =>
outregRd <= '1';
next_state <= incPc5;
when incPc5 =>

if ready = '1' then
instrWr <= '1';
next_state <= execute;
else
next_state <= incPc5;
end if;
when others =>
next_state <= incPc;
end case;
end process;
controlffProc: process(clock, reset)
begin
if reset = '1' then
current_state <= reset1 ;
elsif clock'event and clock = '1' then
current_state <= next_state;
end if;
end process;
end rtl;

]