header file in verilog / a better way to define global constants

Hello, I am working on a verilog project and I need to use some constants parameters in almost all of my modules. So, instead of defining them for every module, I was thinking it makes more sense to have a separate file with all the parameters and constants and include it in each module. However, I am not sure how I can do that. I tried defining them (i.e. defies.v) in a separate file and including it in my module (just like header in C/C++) with `include "defines.v". However compiler is not accepting that and I think, I am doing something wrong.

I would appreciate any suggestion in this regard.