Hello.
The basic cell in Intel FPGA have a wonderful architecture, including dedicated synchronous signals as enable, sload and sclear. However, describe the use of this resources is not easy in vhdl for me. I use "process" only for declare hardware associated whit registers.
Declare "enable" is easy:
if (enable) then --this use enable dedícate port
q <= xxxx;
end if;
Declare "sclear"...
The basic cell in Intel FPGA have a wonderful architecture, including dedicated synchronous signals as enable, sload and sclear. However, describe the use of this resources is not easy in vhdl for me. I use "process" only for declare hardware associated whit registers.
Declare "enable" is easy:
if (enable) then --this use enable dedícate port
q <= xxxx;
end if;
Declare "sclear"...
if (sclr) then
--this use in RTL and Chip Planner a mux! i want sclr dedícate port q <= (others => '0');
end if;
Declare "enable" and "sclear" use two mux. Now don't use
end if;
Declare "enable" and "sclear" use two mux. Now don't use
enable dedícate port.
How can use these precious resourses, synchronous dedícate ports?
Thanks!!
How can use these precious resourses, synchronous dedícate ports?
Thanks!!