Hallo Everyone
I am making a Parallel Flash Loader (PFL) IP core for MAX V device. I have some problems in constraining the design with the timing. In the following link it is mentioned that
https://www.altera.com/documentation...s1458191622012
the following paths should be set as False Path
pfl_flash_access_request
flash_nce
flash_noe
flash_nwe
flash_data
flash_addr
but when i set them as false path, the design is not fully constrained. The time quest analyzer shows that this parts are partly constrained and suggest to add an output delay. I wrote the SDC file in the attachment. Can any one give me any suggestion or solutions on what might be wrong here or if my SDC file is correct?
I am making a Parallel Flash Loader (PFL) IP core for MAX V device. I have some problems in constraining the design with the timing. In the following link it is mentioned that
https://www.altera.com/documentation...s1458191622012
the following paths should be set as False Path
pfl_flash_access_request
flash_nce
flash_noe
flash_nwe
flash_data
flash_addr
but when i set them as false path, the design is not fully constrained. The time quest analyzer shows that this parts are partly constrained and suggest to add an output delay. I wrote the SDC file in the attachment. Can any one give me any suggestion or solutions on what might be wrong here or if my SDC file is correct?
