Qsys, Megawizard: HPC II DDR Memory Controller has different address width, WHY?

Hi everyone,
for a DDR Memory device with bank addr 2 bits, row addr 13 bits and col addr 9 bits I generated a Half Rate HPC II DDR Memory Controller using 2 methods: Megawiz and Qsys.

1. Megawiz: generated IP component has address width of 22 bits, which is expected as described in "emi.pdf"
   For one chip select: width = row bits + bank bits + column bits – 2 = 2 + 13 + 9 - 2 = 22
2. Qsys: generated IP component used in the Qsys sytem has address width of 25 bits, this is what I do not understand.

Could you please explain me what the 25 bits consist of?

Many thanks in forward.

Kind regards,
Hanel