Quartus compile this code without any errors.
Code.sv
testbench.vt
But ModelSim-Altera show error: "Enum literal name 'IDLE' already exists."
Emm... Syntaxis of SV allowed me to use enum in struct but literal scope in struct is still common while registers scope in struct is privat.
Can I write on SystemVerilog two structs in one module and then make enum in each struct with same literal ("IDLE" for example)? Is another struct means another scope?
If not can anyone describe what structs are used for?
If yes can anyone describe to me how to win ModelSim-Altera?
Code.sv
Code:
`timescale 1 ns/ 1 nsmodule test013_LITERAL (
input A,
input B,
output C
);
struct{enum{IDLE,
SOME_STAGE_1} FSM;
logic some_register;
} first_machine;
struct{enum{IDLE,
SOME_STAGE_2} FSM;
logic some_register;
} second_machine;
assign C = A ^ B;
endmoduleCode:
`timescale 1 ns/ 1 nsmodule testbench();
reg test_A;
reg test_B;
wire test_C;
test013_LITERAL DUT (.A(test_A),
.B(test_B),
.C(test_C));
initial begin
#100
test_A = 0;
test_B = 0;
#100
test_A = 1;
test_B = 0;
#100
test_A = 0;
test_B = 1;
#100
test_A = 1;
test_B = 1;
end
endmoduleEmm... Syntaxis of SV allowed me to use enum in struct but literal scope in struct is still common while registers scope in struct is privat.
Can I write on SystemVerilog two structs in one module and then make enum in each struct with same literal ("IDLE" for example)? Is another struct means another scope?
If not can anyone describe what structs are used for?
If yes can anyone describe to me how to win ModelSim-Altera?