I have this bothering me for quite some time now. I make a simple loop with ifs to create a state machine, where I just want stuff to happen in a certain order after some flags are activated.
Something like this:
I'm spying the signals in signal tape and for some reason, sometimes something happen where all the state.stt_... signals are all at 0 making the state machine going out of the loop and my design break. I tried to use a buffer state where I add an else at the end and do state=buf_state. That makes it so the signals go back to the loop, however this wait end up losing some state transitions, since this break seems to happen whenever the is a state change. For example imagine my code was in the idle state it was suppose to go to the one state however it broke and it goes back to the idle, because it never entered the one state.
Has anyone ever encounter that problem? How did you solve it?
Do you see a flaw in the code that could be a cause for this?
Anyway you can help me?
Thanks,
Ricardo
Something like this:
Code:
reg [1:0] state;
parameter stt_idle = 2'b00;
parameter stt_one = 2'b01;
parameter stt_two = 2'b10;
parameter stt_three = 2'b11;
initial state = stt_idle;
always @ (posedge clk or negedge reset)
begin
if(!reset)
state=stt_idle;
else
begin
if(state==stt_idle)
begin
if(...)
state=stt_one;
else
state=stt_idle;
end
else if(state==stt_one)
begin
if(...)
state=stt_two;
else
state=stt_one;
end
else if(state==stt_two)
begin
if(...)
state=stt_three;
else
state=stt_two;
end
else if(state==stt_three)
begin
if(...)
state=stt_idle;
else
state=stt_three;
end
end
endHas anyone ever encounter that problem? How did you solve it?
Do you see a flaw in the code that could be a cause for this?
Anyway you can help me?
Thanks,
Ricardo