Hello,
I am trying to create timing constraints for my design in an SDC, but am having trouble getting 'get_pins' to filter the correct nodes. By that I mean, it won't find any because the names change so significantly during the compilation.
Some, for example those to/from the PLL, are simple to find with Name Finder in TimeQuest, but for others I've had to use the RTL Netlist viewer to track the path of the clock to get the correct pin names.
An example is below. I created a divider in VHDL and instantiated it as ClockDivider with two pins. This was compiled into three components and each of these has a number of pins and by the time I am in Name Finder I am not even sure which one is 'correct' (e.g. if my divider is creating a clock, do I want the data [combout] of Equal0 or [outclk]?)
Capture.jpg
Is there any way to configure Quartus so I can use the names at the 'design level' in my filters (e.g. [*clockdividier|ClkOut])? Unless the net is removed entirely (which would only happen if it wasn't connected to anything, correct?) surely there is some map between these names and the nets post-compilation?
Or is there some proper way to create the constraints that I am missing and am just making it hard for myself? It's just I can't imagine this method working for big designs with hundreds of constraints, or those worked on by multiple people that change often, so there must be a better one.
I am trying to create timing constraints for my design in an SDC, but am having trouble getting 'get_pins' to filter the correct nodes. By that I mean, it won't find any because the names change so significantly during the compilation.
Some, for example those to/from the PLL, are simple to find with Name Finder in TimeQuest, but for others I've had to use the RTL Netlist viewer to track the path of the clock to get the correct pin names.
An example is below. I created a divider in VHDL and instantiated it as ClockDivider with two pins. This was compiled into three components and each of these has a number of pins and by the time I am in Name Finder I am not even sure which one is 'correct' (e.g. if my divider is creating a clock, do I want the data [combout] of Equal0 or [outclk]?)
Capture.jpg
Is there any way to configure Quartus so I can use the names at the 'design level' in my filters (e.g. [*clockdividier|ClkOut])? Unless the net is removed entirely (which would only happen if it wasn't connected to anything, correct?) surely there is some map between these names and the nets post-compilation?
Or is there some proper way to create the constraints that I am missing and am just making it hard for myself? It's just I can't imagine this method working for big designs with hundreds of constraints, or those worked on by multiple people that change often, so there must be a better one.