I am connecting the Cyclone V PCIe Hard IP to the HPS SDRAM memory through an fpga2sdram avalon-mm 64-bit wide interface. This interface seems to look like 4 GB on the FPGA side, even though I only have 1 GB of ddr3 memory. Is there a way in qsys to configure how many address bits are used by the fpga2sdram interface, or will it always be 32?
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