Hi,
When the FPGA is power on and the FPGA does not have any internal configuration.
Is generated automatic the signal DCLK, to load a configuration from an EPCS?
Must I generate it with an external clock?
Regards
When the FPGA is power on and the FPGA does not have any internal configuration.
Is generated automatic the signal DCLK, to load a configuration from an EPCS?
Must I generate it with an external clock?
Regards