Access SPI Slave to Avalon Master Bridge via AVR XMega

Hello,

I'm just going to insert into my QSys system, an SPI slave Avalon MM bridge. MISO / MOSI / SCK / nSS are physically connected to
an AVR XMega. The XMega acts as SPI master.

The QSys contains an Avalon MM Master (VHDL interface to other logic), a PLL and a clock source.

In QSys system is a SDRAM controller included (to access a 32MB SDRAM on my DE0-Nano board).
The address range is 0x0000_0000 - 0x01ff_ffff (read_master and write_master).

The SDRAM-access works well with my VHDL-Avalon MM Master.

I am on the search for a relevant documentation, and examples, that describe howto the access the memory
area of the SDRAM controller via SPI.

www . altera . com / literature / hb / nios2 / external_processor_if.pdf (page 11-12) explains that this is possible.

It is not my problem to send or receive data via SPI (in my XMega firmware).
My questions are how do I set one avalon addresses via SPI? How data can be read via SPI?
How are the data packets look like? Is there a protocol for this purpose?

Maybe i missed something.

Kind regards
Kai