Hello everyone,
I am using the BeMicro CV Development Kit board which is based on a Cyclone V
Device 5CEFA2F23C8N. I am using Quartus II 64-Bit Version 13.1.0 Build 162
( problem also occurs with Version 14.0 ) and I am hanging in 2 problems:
1) sometimes after downloading the elf file: Note: The problem occurs always
if an external PLL is used:
Verifying 08000000 ( 0%)
Verify failed between address 0x8000000 and 0x800D71F
Leaving target processor paused
2) Reset problem: the reset does not work at all even though I followed the instructions
http://www.altera.com/support/kdb/so...072011_71.html
The board will be dead if I press the reset button.
Enclosed, please find all the referece files. The myload.sh script in the flash directory
will load and start the test programm to the BeMicro CV board. I have testet 5 boards already
with the same result. Can anyone confirm that there is a problem in the CYCLONE V which is
clock/PLL related. If yes, is there a fix available ? or did I make a mistake in my qsys design?
Many thanks in advance
Reinhard
I am using the BeMicro CV Development Kit board which is based on a Cyclone V
Device 5CEFA2F23C8N. I am using Quartus II 64-Bit Version 13.1.0 Build 162
( problem also occurs with Version 14.0 ) and I am hanging in 2 problems:
1) sometimes after downloading the elf file: Note: The problem occurs always
if an external PLL is used:
Verifying 08000000 ( 0%)
Verify failed between address 0x8000000 and 0x800D71F
Leaving target processor paused
2) Reset problem: the reset does not work at all even though I followed the instructions
http://www.altera.com/support/kdb/so...072011_71.html
The board will be dead if I press the reset button.
Enclosed, please find all the referece files. The myload.sh script in the flash directory
will load and start the test programm to the BeMicro CV board. I have testet 5 boards already
with the same result. Can anyone confirm that there is a problem in the CYCLONE V which is
clock/PLL related. If yes, is there a fix available ? or did I make a mistake in my qsys design?
Many thanks in advance
Reinhard