DDR3 memory controller in Cyclone V

Hi, I am new to DDR3 memory controller design. I have a cyclone V development board. I fired up the IP tool and generated a DDR3 controller. This is whwer I am having a problem. How do I interface the AVL signals to the rest of my system? I have been digging around the internet, and it looks like I need logic to go from 64 bits(controller) to 16 bits (my logic). To further complicate matters, there is no good documentation on how to do this.