regarding DE0_NANO_QSYS.v file in Quartus II v13.0

Hi all,

While working on DE0-Nano board as per the My_First_NiosII_Qsys user manual, the DE0_NANO_QSYS/Synthesis/DE0_NANO_QSYS.v file has not got changed as per page No: 58 (input & output wire assignments) in My_First_NiosII_Qsys pdf document. Kindly confirm whether the following parameters are to be changed manually in DE0_NANO_QSYS.v file even after generating the required system contents in ‘Qsys’ of Quartus II, 64-bit, version 13.0

1. clk_clk,
2. reset_reset_n,
3. pio_led_external_connection_export

Please refer the attached snapshots for more details and kindly help in this regard.

Thankyou

- Babloo

Attached Images

• Veilog HDL file.jpg (198.8 KB)
• DEO_NANO-QSYS Veilog HDL file.jpg (427.7 KB)