Hi all,
I'm a complete newbie in Verilog, so I have a question.
I have in my main Verilog file (irrelevant code stripped out):
Now, Default.id7seg_display_export is declared as:
My question is, how do I connect individual bits from id7seg_display_export to the different HEX outputs signals? I just can't figure it out because I don't know the syntax...
I'm a complete newbie in Verilog, so I have a question.
I have in my main Verilog file (irrelevant code stripped out):
Code:
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module Lab2(
//////////// SEG7 //////////
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7
);
//////////// SEG7 //////////
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
Default u0 (
.id7seg_display_export (???)
);
endmoduleCode:
output wire [27:0] id7seg_display_export // id7seg_display.export