I am trying to create a frequency doubler using an Xor and a DFF. However it requires a delay cell to create finite pulse width for the signal. I am using functional sim. Does the cell exist in the library? if not, how do I generate one?
I need to be more precise in my question. I can edit the VHDL file and add the "after" command". How do I ensure that Quarta II will synthesize the delay properly? Unfortunately I have given up on the timing simulation after three days. A veteran of FPGA commented earlier that it is easier to build the design than spend time on timing. So i plan to go that route. However that does not solve my delay question. Thanks for your help.
I need to be more precise in my question. I can edit the VHDL file and add the "after" command". How do I ensure that Quarta II will synthesize the delay properly? Unfortunately I have given up on the timing simulation after three days. A veteran of FPGA commented earlier that it is easier to build the design than spend time on timing. So i plan to go that route. However that does not solve my delay question. Thanks for your help.