Writing values into memory and reading those values. Timing Issue!!!

Hi,

I am trying to design a memory (logic [7:0] memory [0:31]) in system verilog. First I write 0s into all the address of my memory, then I read one by one. After writing 0 into the address memory[31], i start reading from memory[0]. But i am getting x. I think there is some race condition or setup time violation. Please help me with this.
Dont get confused with the system verilog constructs. I just want to know how to fix the timing issue here.

Here is my code:


module mem_test(input logic clk, output logic read, write, output logic [4:0] addr, output logic [7:0] data_in, input logic [7:0] data_out);timeunit 1ns;timeprecision 1ps;bit debug=1'b0;//logic [7:0] rdata_out;task write_mem(input logic [4:0] waddr, input logic [7:0] wdata_in, input logic debug); @(negedge clk) begin addr <= waddr; data_in <= wdata_in; write <= 1'b1; read <= 1'b0; end unique if(debug) begin $display("addr=%b, data_in=%b", waddr, wdata_in); endendtasktask read_mem(input logic [4:0] raddr, input logic debug); @(negedge clk) begin #10 addr <= raddr; read <= 1'b1; write <= 1'b0; //#2 rdata_out <= data_out; end //rdata_out <= data_out; unique if(debug) begin $display("addr=%b, data_out=%b", raddr, data_out); endendtask initial begin//genvar i, j, k, l;for(int i=0;i<=31;i++) begin write_mem(i,8'd0,1'd1);endbegin for(int j=0;j<=31;j++) begin read_mem(j,1'd1); endendfor(int k=0;k<=31;k++) begin write_mem(k,k,1'd1);endbegin for(int l=0;l<=31;l++) begin read_mem(l,1'd1); endend#500 $finish;endendmodule