usb blaster for windows 7
hi i have installed Quartus II subscription edition version 8.0 for windows (platform supported windows vista,xp, 2000) on windows 7 operating system...i tried some project in vhdl which works...
View Articlecreate megawizard components without megawizard
Hello all, I am trying to do as much as possible with the commandline and tcl scripts. Now I know it is possible to create some already defined component with the megawizard, but I don't know how to...
View ArticleDE0 Nano With 9 Degree of Freedom Razor IMU from sparkfun
Hi All, Just out of curiosity has anyone used the 9DOF Razor IMU from sparkfun with the DE0 Nano. I am creating a UAV as a project and would like to integrate many more peripherals with the Nano, this...
View ArticleQuartus ii 13.0 on Fedora 17, Qsys wont run
Hello, I have installed Quartus II Version 13.0 on fedora 17 (after many library Upgrades and installs) . ANyway Quatus start no problem now, but when I try to start Qsys, I flash for about 30 seconds...
View ArticleEPCS selection for Cyclone V
Hi all! Please help to choose epcs device for configuration 5CEA4U15. We need minimum size package of EPCS, because we have limited space on board.
View ArticleUsing Single Port Ram module in a parent module
I am trying to use the RAM 1-port mega function in an upper level module but I can't find any examples how to use the RAM module once it is attached. Everywhere I see how to instantiate it, but once...
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Cyclone 5 Custom PHY rx_datak
Hello, I'm having some difficulty in getting a Cyclone 5 Custom PHY design to properly align to an incoming 8B/10B stream. The design consists of three channels running around 2Gbs with the following...
View ArticleCan't install Quartus web 13.0 on CentOS 6.3
Hi, I have successfully download the package, and I attempted to run the installation procedure by running the setup.sh script, but it nothing seems to happen - I am brought back to the shell prompt...
View ArticleCan't get my do while loop to repeat
Here is a sample of my code, I'm trying to make a prompt for a user enter 1 for reset test, 2 to do something later, and 3 to exit. After pressing 1 the reset code executes, the code should then reask...
View ArticleModelSim AE 10.1d Error
I've recently been given a trial ( eval) license for ModelSim AE. I am able to open and run, compile and load libraries but when it goes to execute the vsim command I get the following: # ** Error:...
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Connecting SEG7[63..0] bus to HEX7..0 pins
Hi all, How do we connect the seven segment display pins to the HEX pins? I have tried the above method but it gives the following error: Error (275021): Illegal wire or bus name...
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PCI testbench verifying....please help...
Guys, I have created myself a PCI testbench for verifying home made PCI card, Can anyone give idea if I'm doing in a right way or not ? I'm following the paper "Interfacing PCI with FPGA" The port is...
View ArticleQsys PCIE Hard IP
Hi, In Qsys, what is the difference between IP compiler for PCIe Express and Cyclone V Hard IP for PCIe express? Thanks. Regards, Aristotle
View ArticleCustom Phy with stratix V GS
Hi, How to configure Custom Phy's for 10G settings. I am using Stratix V GS (5SGSMD8N2F45I2N) with transceivers, I am in search of the best xcvrs for high speed optical transmissions. If custom phy is...
View ArticleSimple Socket Server Template can't find mac adress?
hello, I am using Simple Socket Server Template for my own triple speed ethernet qsys system in which I modify the NiosII Ethernet Standard Design by replacing DDRx with ssram on my CycloneIV GX150...
View Articleproblem with size of sof file
I'm using quartus II, in my project I have a sof file of a size of 2412 Ko, I don't even modificate anything in my quartus direcotry project and when I start assembler to generate a new sof file, I...
View ArticleQII 12.1 Ubuntu 12.04 QSYS Avalon ALTPLL problem
In QSYS trying to add an Avalon ALTPLL module the operation fails. The init windows pop up rapidly but the window to set parameters doesn't come up. QII 32bit or 64bit has same behavior. Other modules...
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EPC20, VHDL Divider & PLL Question
Hello, Not sure if this is the 'correct' sub-board in which to post these related questions.... I'm a newbie student of FPGAs and VHDL. My setup: 2.6 GHz AMD-64 with 4 Gigs of RAM WinXP Pro SP3 Terasic...
View ArticleElf2Flash problems
I'm trying to convert the NIOS II executable .elf file into .flash file with the Elf2Flash NIOS II EDS utility (v.9.1). My .elf file contains two differents .text linker regions. The first one...
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how to ENABLE/DISABLE parts of an IP-core depending on the instance parameters??
Hi @all, if have already posted this question in the following thread: http://www.alteraforum.com/forum/showthread.php?t=40155 (post #3) and i think it is worth starting a new thread for discussing...
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