access to usb device in serial way
I want to connect FPGA to PC with usb device, but most applications access devices by serial (COM port). Is that possible let usb device appear asan additional COM port? Thanks!
View ArticleWhy the type converter does not work ?
In my design I need to do is convert a std_logic_vector signal to the integer signal for array index. Then I do following: " use IEEE.NUMERIC_STD.ALL; generic ( C_SLV_ADWIDTH : integer := 6; -- This...
View Articlewhere have documents for writing VHDL of optical fiber port chips
where have documents for writing VHDL of optical fiber port chips
View ArticleHow to measure the speed for ethernet port
How to measure the speed for ethernet port for example, how can i confirm that it is using 1000M, 100M or 10M
View ArticleWill Cyclone / Arria support OpenCL in the feature?
hello friends, In the past we run our application on AMD GPU by OpenCL and it works fine. but it need much power and noise. Since Stratix is too expensive for our custmer, we'd like to know, the Ariria...
View ArticleStratix 2 GX Transceiver Development Kit instalation
Hi. I have Altera Stratix 2 GX Transceiver SI development kit based on Stratix 2 GX EP2SGX90EF1152C3 chip. But I have no software for it. I hope you could help me with getting it. Software that i need:...
View ArticleQuartus and Nios2 on Linux via ssh
*, I would like to execute fpga builds over ssh. Our toolset is Altera Quartus/Nios2 EDS 10.1. I am able to build when logged into the Linux pc. It seems that X is required for the tools to work...
View ArticleVerilog: FFT With 32K-Point Transform Length --- sfftmodel can't be found!
I got the sfftmodel.mexw32 file from altera's website, and simply changed the extention to .dll. My computer is of 32 bits, but I keep getting the error message: tsfftmodel.dll can't be loaded...
View ArticleSPI core in nios ii
hi, I am using spi core to configure registers of clock chip generator cdce72010. when i read back values from the registers of the chip i get a junk value first, then again when i sent a command to...
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Sof file doesn't work
Hi, I'm working with Quartus II, using a Cyclone III device with a EPCS64 flash memory. I've inherited of a Quartus project, I have a sof file of 2412 Ko called top_fpga_opg_master.sof of type EP3C80....
View ArticleProject 1- Fully associative cache
Hey guys, i'm studying computer engineering and I got a project to do in Quartus II. The project is about a Fully Associative Cache designed in quartus II (schematic Design ) with 3 specifications: 1-...
View ArticleProblems with OpenCL SDK 13.0 on Windows 7
Hi all, I've recently upgraded to OpenCL SDK ver. 13.0 on Win7/64 (2x Xeon + 64GB RAM) After the installation (Quartus + OCL SDK) I tried to compile the moving average design sample with: "aoc --board...
View ArticleCyclone V DS5 Eclipse Errors
Has anyone else noticed that they get errors in the Eclipse view but when looking at the compiler console it all passes? I am able to make .axf files etc.. but still DS5 says I have errors, any ideas...
View ArticlePci device detection issue
Hi Sir, We are facing an issue with PCI mega core function. The issue is “processor detects two PCI target devices even though one PCI target is inserted in the PCI slot”.Can you please provide any...
View ArticleAlt up audio library and WAV files
This problem is something I have been stuggling with the last few days. The project I am doing (for school) involves making a music player with VGA output and keyboard input. Audio is supplied on a SD...
View ArticleError in creating flash files-**Error in creating intermediate files **
Hi Friends , I'm getting error while generating flash files using sof2flash command i used "sof2flash --input=TR4.sof --output=TR4_hw.flash --offset=0x00020000 --pfl --optionbit=0x18000...
View ArticleWhat is the way to lead the OpenCL SDK compiler to reduce kernel logic...
Hello friends, I am working on implementing a video processing design on an FPGA using OpenCL . When generating reports for my design,I get 40% of logic utilization and 23 Mworkitems/s as throughput...
View ArticleUnloading Packet
Hi I am making a video application witch receives UDP packet from a sender on my computer. I receive the packet just fine with the rcvfrom function using the nichestack. Now i need to send these packet...
View ArticlePCIE IP - Relation between PCIe core clk with the other signals?
Hi all, I am using PCIe IP in my QSYS system generator in Single word completer , Completer only mode. I am facing so many clock problems in the design and i want to sychronize our design with the PCIe...
View Articledevkit startix5 pcie-demo issue
Hi all, i tried to run demo pcie example that shipped with kit but it stall at ltssm: detect.Active !! , i know that was issue at ACDS less than 12 , but i'm using 13 the example provided use hard IP...
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