Analyzing Simulation result
Hello Friends, Am new to the Quartus II environments, but i like to know what a the specific part of the software one should go to and dwell on in other to analyse simulation result or output.
View ArticleAccessing HPS Pins
Hello, I know I can route HPS pins to the FPGA side but is it possible to do the opposite, route FPGA side logic to HPS part pins? Thank you
View ArticleCustom instruction to access SDRAM
Hi, I'm inexperienced with FPGA's. I want to implement a custom instruction, which calculates an SDRAM address and writes something into. I use NIOS II e and SDRAM controller IP. My questions are: 1....
View ArticleQaurtus GUI comamnds dump
Is there a way to ask Quartus GUI to dump all the comamnds that it runs from begining to end of process when it generates a SOF file? I want to make a script to automate compile process.
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problem (?) using shared variables
Hi, I need your kind opinion. Please, anyone explain me why the following code is not running. VHDL code (sel-explainable) Code: ------------------------------------------------------ entity...
View ArticleARM DS 5 script to initialize and load code in SDRAM
Hi, My question is regarding the HPS core in Cyclone V SoC. I have successfully built and run sample code that came with ARM DS 5 using USB Blaster II interface. The code by default runs on 64K scratch...
View ArticleQuartus II JTAG Server Error Code 89
I've been trying to program my DE0-Nano for over an hour and a half now, and I am always getting an error when I press start in the programmer: Code: Info (209060): Started Programmer operation at Fri...
View Articledata transfer from fpga to hps
Dear all, i am using Altera SOC (Cyclone V) development board for my project. This board is receiving data on its GPIO (which is connected to FPGA side) at the rate of 27 MHz. It is continuous stream....
View ArticleError CODE VHDL in Structural model
Hi All. I am new VHDL and I see a error when coding: Can YOU help me! Error (10348): VHDL type mismatch error at DDS_test.vhd(37): type of formal parameter "out_cos" does not match port type of value...
View ArticleVhdl ams supported kit
Is there any FPGA kit which supports VHDL AMS for developing ADC on it
View Articlehalf-band filter
I am trying to implement a half-band filter in Verilog. The questions are: 1. what is the definition for a half-band filter? Is it the same as what we have in traditional multi-rate DSP...
View Articlehalf-band filter implementation
I know this is typical in signal processing implementation. Therefore, is there already an example on how to implementation a half-band filter in Verilog? Thanks in advance.
View ArticleData cache flush guaranteed to complete before returning?
Hi, I'm working with a multi nios-ii implementation where there is a shared off-chip memory bank. Access to the shared memory is protected with a mutex across the CPUs and the DCACHE is enabled on the...
View Articlejudgement on whether or not there is an overflow
I have 3 numbers x, y, z to be added together, each with the format of s1.14. Then the sum will be in the format of s3.14. How to make judgement on whether or not there is an overflow? If it is judged...
View ArticleError evaluating 'PreSaveFcn' callback of Input AlteraBlockset block
Hi, I have installed the latest Quartus II with the DSP Builder, combined with the 64-bit version of MATLAB R2013a (8.1.0.604). The operating system is Ubuntu 12.04. As much as I can see, all building...
View ArticleCIC filter in VHDL
Hello all, As in title, I want to realize CIC filter written in VHDL. - specifications of CIC filter > clock : 50 MHz > decimation rate : 500 > output freq. : 100 kHz > output word width :...
View Articleipcore simultae in modelsim
hi, there are ddr 、dma and other self_written master ip in sopc ，i want to know how can i simulte the system in modelsim . if i need to write testbench for singal ip or for the whole , right now i load...
View Articlewhat should i replace with question mark?
hi every body this is my code Code: architecture structure of main is ..... begin L1:for s in 0 to N-1 generate L2:for t in 0 to 2**s-1 generate...
View Articlefetching input signal to ADC in DE2 board
i am doing the speech recognition project in DE2 board, and i am suffering how to apply a ADC into DE2 board, so i need to write a Verilog code? and how to read the input signal from microphone? anyone...
View Articlejtagserver - documentaion for client side interface
Hi Probably a trivial question for those, who know, but somehow I can't find the answer via "Search Altera" engine. Is altera jtagserver client-side interface documented? I'd prefer documentation at...
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