How to enable dual core cortex A9 mode of Cyclone V?
I have used Cyclone V in Single Core configuration but i don't know how can use it in Dual core mode. I have checked the reference manual where i can only see HPS Info Register. This register indicates...
View ArticleConvolutional Interleaver: strange behaviour, any advice?
Hi, I'm developing a communication system emulator for educational purpose (university project). Now I'm blocked with the Interleaver and Deinterleaver modules I have written using Verilog. I...
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Rising Edge Problem in FSM
Hello, Since I'm a beginner, I need some advice. I was working with one input first, when I added my second input ,"Dash", it got complicated and I'm stuck. My states change depending on two inputs....
View ArticleHow can i read Jpeg image from SDCARD with using University program SDcard...
I dont have any idea to read JPEG image from SDCARD and how can view it on VGA. I have tried for text file. It successfully created it in SDCard and also i can read the text file from SDCard then after...
View ArticleTerasic DE1-SoC availability?
Hello Does anyone know when the Terasic DE1-SOC (at de1-soc.terasic.com) will be available for purchase? Even on their web page the 'order' sub-page is pretty much blank. I guess in the following weeks...
View ArticleDdr2 and vga
hi i am new to using quartus v13.0. i wanna build a video interfacing system using dsp cyclone 2 ep2c70f672c6. to create a core in sopc builder in quartus 2 v13.0 i cant find vga controller for...
View ArticlePowerplay Power Analysis
Hi! I'm new to FPGA programming and me and my classmates are trying to analyze different adders in Quartus II. We cannot really obtain any good results in the power analyzer because we are trying to...
View ArticleUsing VIP suite for Up-Scaling.
Hello, I am using VIP suite and SDI Ip core for converting DVI video input to 3G-SDI video output for sending video to long distance (150 mtrs). For the input DVI resolution 1600X1200 @60Hz,...
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system ID mismatch nios 2 bemicro sdk
Hi everyone, I am doing tutorial for Bemicro sdk SW lab. When I try to click "Run configurations" and "refresh connection" in "target connection" tab, I got system ID mismatch error.sys_id_mismatch.jpg...
View ArticleExternal Interface-like connection HPS to FPGA
Hello all, I am trying to find a way to connect the HPS to the FPGA logic using an interface similar to those external interfaces which can be found in microcontrollers. Something with an address and...
View Articlecreate an interrupt QSYS
Hello, I have a problem in my project and i'd like some advice. I have created a program which just copy the state of push button on leds (development kit cyclone 4GX). Until here, it's working. Now i...
View ArticlePotential Quartus Fitter Issue with Mixed Voltage Pins on Cyclone V
I am working on a Cyclone V design that is utilizing most of the pin resources. In my first pass, I let the fitter automatically assign pins. The issue that kept coming up is that, if not mitigated,...
View ArticleQuartus II not compiling
When I try to start compilation or start analysis & synthesis nothing happens. The compilation report comes up immediately and the Flow status says successful, but the date is wrong. I can even...
View ArticleAndroid Port for Helio View kit?
I recently started some proof of concept designs using the Helio View kit (http://www.macnica-na.com/web/americas/heliokit). I was wondering if anyone had ported Android to this kit yet?
View ArticleUsing PLL "lock" signal as the async reset in Verilog
If I want to use the PLL "lock' signal to work as an async reset, the "lock" signal will keep low after the FPGA is powered and goes high after a duration. If I won't reset my PLL, then it means "lock"...
View ArticleProgrammin the EPCS64 in the DE0-nano
I am having trouble programming the epcs64 configuration flash in the DE0-nano dev board. I have read an followed the instruction in the user manual for the board. I have successfully programmed the...
View ArticleO3 Optimization features
Hi , I just wanted to know the impact of O3 optimization flag with the aoc compiler... The logic utilization seems to increase with O3. What are all the features of O3 ?
View ArticleCyclone IV EP4CE22F17C7N example codes, tutorials
Hi everyone, Is there any tutorial or example codes for FPGA Cyclone IV EP4CE22F17C7N beginner? I am looking for sample examples like flashing LEDs, GPIO usage, ADC, DAC, interrupts, PWM, etc. I have...
View ArticleTsw1400----- for other applications
Hi, I have a TSW1400EVM for Stand Alone application so called Data Patterning. This kit has a Stratix IV FPGA. I Want to use it for other applications, But I have Issues with Clocking my own...
View ArticleHow to find Macrocells number of a CPLD
Hello, I want to know Macro cell number of a CPLD device (EPM, EPF, EP1M family). Can i get it from Data Sheet or Ordering code of a device.
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