Anything wrong with this code for using CRC generator
first time to use CRC generator from plugin 1. i am not sure whether assign 0 to reset_n 2. when payload more than 32 , does it mean to set endofpacket 0, until final 32 in payload , set it 1 3. i am...
View Articlehow to use alphabetic words instead of hex number in payload of frame for...
does it mean that need to write a function to convert alphabetic words into hex number and then assign to payload? can i assign alphabetic words to payload in ethernet frame for tx_data in ethernet?
View ArticleTutorial Video: How to boot uClinux on NIOS II Processor with MMU
Hi everyone I record a tutorial video about how to boot uclinux on Nios II Processor with MMC I used DE2-115 as reference but you can use any board that you like Feel free to contact me if you have any...
View ArticleProblems with generating a flash file with elf2flash
I seem to be having issues using the Flash programmer to burn my elf and sof file into flash so it can boot from this location. I have a couple of questions. I have read and followed the documentation...
View Articlesingle_port_rom .hex initialisation file
Hi, I added a single port rom entity to my VHDL via "Edit" --> "Insert Template". I specified the initialisation file as "rom.hex", but it is initialising using a MIF file. The MIF filename has been...
View Articlestd_logic_vector type does not match integer literal
Error (10517): VHDL type mismatch error at Transmit2.vhd(118): std_logic_vector type does not match integer literal at constant preamble : STD_LOGIC_VECTOR (31 DOWNTO 0) := 16#55#; -- 16 bits * 2 = 32
View Articlewhat should be input to address in MAC control interface
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); it is only 8 bit 32 bits is for 2 hex but mac address has many hex number so what should i input to address in MAC control interface?
View ArticleHow do we see the placement & routing on the FPGA chip
Hi, How can we see the actual placement and routing and/or where our design elements are placed on the FPGA using QuartusII ? I have synthesised a design on CycloneIII and want to see where the design...
View Articlehow many nanosecond used for after for ethernet to send 32 bits one by one
i harded code with counter to send a ethernet frame, any alternatives to do smartly? if using after x ns, how many nano seconds i use for this and how? Code: process(clk) VARIABLE last_clk :...
View ArticleQuestion about the PCIE descriptor format
Hi, I am trying to test my receiving and transmission logic which connected to the PCIE megaCore function. Currently, I just wanna to test the functionality of my top wrapper function, so In my...
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Errors of sys generating in SOPC Builder
Nodes of "Altpll" are missing source Files including all PINs, showing in the following image. 130317172153.jpg Ive rebuilt the whole project completely as the...
View ArticleErrors of sys generating in SOPC Builder
Nodes of "Altpll" are missing source Files including all PINs, showing in the following image. 130317172153.jpg Ive rebuilt the whole project completely as the...
View Articlevariable declared outside subprogram or process must be shared variable
variable set_10_external : STD_LOGIC; declaration error, variable declared outside subprogram or process must be shared variable already declared a variable, got error, isn't it shared variable Code:...
View Articlehow to get part of variable of type std_logic_vector like substring function
for example temp : std_logic_vector[31 downto 0] just want to get starting from 3th bit to 5th bit and store to another variable of type std_logic_vector[2 downto 0] like offset how to write in vhdl?
View Articlestop processing at 2% like a hang
https://skydrive.live.com/redir?resi...71C68BE47C!328 i write a project after compile, it success, then start processing but stop at 2% what is wrong with this? when i run it, it just continue consume...
View ArticleInitial Register Value
Hi Guys, I would like to ask the next question. The first one: Is it synthesizeable to determine value, such as 50000(integer), during reset (one step before "clk'event and clk..." line)? *** if(reset...
View Article2 FFs synchronizer constraint
Hi, I am using a 2 FFs synchronizer in my design, and it requires a constraint that tells quartus to place the 2 FFs as close as possible to each other. how do i set this constraint? is it in the sdc...
View Articlepc to altera gx transc
hello i am trying to learn how to use the stratix gx transceiver i would link some info on the gigabyte ethernet mode if it can be used to transfer data from PC to fpga how is it done ? and where can i...
View ArticleFPGA screen problem; Time requirements not meet
Hi everybody, I read the similar subject here but I didn't find the solution of my problem. I have an image processing project, I'm sure that there isn't any error in algorithm and files which I added...
View ArticleAltera Quartus Linux 64bit
hello, I'm trying to setup altera quartus web edition 9.1 sp2 on my 64bit arch linux machine. I have set the PATH variable to include the bin/ directory. When I now call quartus from the regular bash,...
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