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using PFL in MAX II and MAX V
Hi, guys, recently, I am studying to use PFL in max cpld for FPP configuration of FPGA. I found that when I used PFL in max v 5m570zt100c5, the time requirement was not met (Fmax was less than 30mhz),...
View Articleproblem with Clock Constraint 3 bit modulo 5 counter
Dear Guru, You may refer to the link as I posted the same question before at: Forum > Coding Questions > Verilog and System Verilog > simple Infinite loop expansion header using Altera DE2-70...
View ArticleFace Recognition Algorithm Suitable for Hardware Implementation
Dear All, I am a student and currently doing a project in which i have to implement an algorithm on FPGA using Verilog HDL or C++ langugae (necessary conditions). I have searched on internet and found...
View ArticleError while Compilation of code in Quartus II 9.0 Version
My project is "Implementation of Advanced Encryption Standard". In that I'm running QPF file of my project code & I found following errors. Error: Tcl error: can't find package :: ddr :: settings...
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NIOS II memory writes failing - values being input at wrong addresses (I2C...
Hi, I'm trying to integrate an I2C core from opencores to my Cyclone IV device. Apparently the version I'm using should just drop into the SOPC and work after being wired to some outputs...
View ArticleBoard testing problem for FIR filter
Hi everyone, I'm testing a Band Pass Filter generated by altera IP core (FIR compiler) on the board having Stratix 5 device 5SGSMD5K2F40C2 . I have written a small top entity for the BPF where in I...
View ArticleIP core student version ?
Guys, Is there any IP core with student version and low cost one ? Thanks
View ArticlePCI express Stratix IV implementation
Hi there, I'm using a Stratix IV GX and i want to use the PCI express link to transmit data from my FPGA to another one. The data which have to be sent are generated by a personnal IP and no need for...
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Image error
Hello, i'm trying to display an image on a screen using the vga controler but the pixels of the image does not appear in the right posision. Here is what i've made in the SOPC.sopc.jpg If anyone knows...
View ArticleMulti Touch LCD Interface with Altera DE2
I am trying to use the Terasic Multi Touch LCD display with an Altera DE2 board in Quartus II 11.0 and the Altera Monitor program. There was a previous thread on this but it was not very informative....
View ArticleMoving LogicLock regions to another
I am totally beginner; so I am sorr if my questions are naive: 1- I want to move LABs from the Root Region to my defined Region in another location 2-my second question is that whether the critical...
View ArticleMultiple Constant Driver Error
My VHDL is a little rusty and I'm trying to get back up to speed but I've run into a problem with the code below and can't determine the source of the problem. In short, I've generated an array of...
View ArticleQuartus/Timequest and extended temperature
For Cyclone III (EP3C10F256), Quartus does not show any industrial-temp versions as "available devices". The Tech Bulletin Extended Temperature Support for Cyclone II, Cyclone III, and MAX II Devices...
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Problem when downloading zImage to DE2-115
Hello altera forum, I have been currently working with DE2-115 using uClinux for over 4 months now, and all this time me and an student which is finishing his master degree, have been passing through...
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nios2 iss problem/bug
Hello, I am tryign to run the nios2-iss from thet command line and have run into a problem. Here is what ive tried: Code: $cat main.c int main() { return 0; } $nios2-elf-gcc main.c...
View ArticleIOE Programmable Delay
Hello, The data sheets for the FPGAs list the IOE programmable delays as follows (generic example): Parameter: D1 Available Settings: n Min Offset: 0 Fast Model: x ns Slow Model: y ns Could someone...
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Vending Machine Controllerusing VHDL and Logicworks 5
Vending Machine Controllerusing VHDL and Logicworks 5 This is my final project of a Digital System course. I am very unfamiliar with VHDL and my team members, teacher and TA have not been able to...
View Articlesimulating nios ii software
i have developed an application in nios sbt. i want to simulate it. i dont have any target hardware platform. so is there any way i can simulate my application?
View Articlealtserial_flash_loader shared access
I've been trying to get both the JTAG indirect flash programming and a user design utilizing the SPI interface to work. Both cores work independently. I am feeding dclk_in with a 20MHz output of an...
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MicroC/OS-ii component invalid
I stumbled upon an error while doing my project, when i open the properties for my project, it stated that the microC/OS-ii component is invalid. This cause my project cant be built due to missing...
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