altera DMA stuck in busy state
Hi, I was trying to transfer data between DDR and FPGA through DMA(normal DMA from Qsys) in arria 10 devkit. The DMA goes into busy state after the transfer is initiated but doesn't come out of it....
View ArticleArria 10 memory simulation
Hi, I'm trying to use ModelSim to simulate a small design in Arria 10. Design is a counter driving a ROM. Quartus 17.1 compiles OK. ModelSim Error (copy & paste) # ** Error: (vsim-3033) nofile(38):...
View ArticleHardware acceleation of a custom software
Hi all, My name is Vivek Gujari. I have a custom built software in C# (approx. 50k lines of code) in visual studio. I want to design a near real time system by accelerating the algorithms of the...
View Articlepragma unroll breaks kernel
Hi, I'm trying to figure out why my kernel breaks when I try to use the #pragma unroll statement for a loop. I'm using the 16.1 SDK and the device I'm running on is an Arria 10/DE5a-net and compiling...
View ArticleUART0 register access from System Console
Can someone tell me how to access the HPS UART0 peripheral registers using the System Console? My setup: Custom board with Cyclone V SoCBoot all from SD (SPL, U-boot, Linux) I do not see any characters...
View ArticleHelp me find camera module for Deca max10
Hi, I cant seem to find any camera module that fits this board. The evaluation did not come with a camera, but i found that a complete kit was sold once. The kit included an ar0833 camera. I also found...
View ArticleAcademic Q: Why doesn't Quartus Synthesis Allow Some Restricted Classes?
Was pleased to discover SV supports scalable tasks/functions to the extent that if you bury it in a class you can set the 'type' by parameter. Why then can't this be synthesized? For example, why can't...
View Articlelow speed on hps to fpga bridge
hi , i successfully implemented s system which is working on linux. my qsys system consist of a custom component running at 10khz ( output of a counter passing to hps (32 bit)) and hps (with only light...
View ArticleMemory WRITING issue
Dear, I have a procedure (Sort) that read two numbers in each cycle. and return the max and the min. I am reading two numbers from mif file , the problem is that I want to write back the result...
View ArticleDE10-Nano Kit vs DE0-Nano-SoC Kit/Atlas-SoC Kit : Which to procure?
Background : I have no prior experience in FPGA SoC or FPGA or CPLD however I have worked extensively on Raspberry Pi 3 Model B (Raspbian OS) and ARM M4 micro-controller (Bare Metal Programming). I...
View ArticleImplementation of a code only using 2:1 Mux
Hii Everyone, I am using Quartus Prime Design suite 15.1. I wrote a behavioral verilog code. When I compile it and see its netlist using Tools->netlist viewer->RTL viewer, I see the code is...
View ArticleProblem with tcl automation script
Hi. I want create a TCL script which will be write into log file after compilation current revision of a project, current timestamp, current active signaltap file name and current revision ID. I have...
View ArticleCyclone 10 LP : VCCA Voltage
Hello All! I have a new design with Cyclone 10 LP family. I would like power the VCCA pins to 3,3V, but is not clear to me if it's possible. In the "Cyclone 10 LP datasheet", C10LP51002 Table 1, says...
View ArticleIntel HLS (High Level Synthesis) compiler
Hello all, Can anyone please tell me from where to find some of the sample examples/projects of Intel HLS compiler ?
View ArticleBuffer chain output from DLL in ALTDLL
Hi, I require clocks with different phase shifts. Theoretically, the outputs at each stage of the buffers in the buffer chain of DLL in ALTDLL megafunction should do it. However, ALTDLL outputs only...
View ArticleRun Functional Simulation Error
I've just installed the QUARTUS II, and i am trying to run a simulation because i'm receiving the message below, can i have help solving this please? thanks Device family: MAX7000S Running quartus...
View ArticleProblems to program Cyclone V GT FPGA
Im new using Altera boards I have two questions. I check the Quartus_II_Introduction for verilog users. On the programming chapter it says that "DE0-CV, DE0-Nano and DE2-115 Boards" should have a...
View ArticleAltera cyclone 5 is not booting from spi
I created one uart program in quatux 2,i added uart in qsys,on chip memor and serial flash loader .i compiled it in quarux 2 .it succesfully compiled.when i opening this project in nios and create new...
View ArticleExternal SPI master clock connect to CPLD global clock network ?
When using SPI communication, where a CPLD is acting as the slave and a microcontroller is the master, would the SPI clock (SCK) be connected to a global clock network of the CPLD? I.e. one of the CLK...
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NIOS II Command Shell not working
Excuse me if I this is a dumb question I am brand new at trying to use the NIOS II SBT. I am running Quartus Prime 17 on Windows 10 and keep getting an error when trying to open the software build...
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