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Locking period of a Femto crystal to give a stable output frequency

January 16, 2014, 10:45 pm
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Hi all,
I'm working on PCR, so i'm using a femto crystal to generate 27MHz frequency by controlling the duty cycle passed to the crystal.
I wanted to know how long will it take for the crystal to produce a stable frequency upon supplying a certain duty cycle.
The crystal is a Femto clock VCXO ICS810001-21.
Thank you,
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Sine wave manipulation

January 17, 2014, 4:22 am
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Hello everyone,

I have a project where i have to do the adc conversion of sine wave. From there I got a 16 bit output. now i want to detect the tip(peak or crest) of the sine wave, for this I wrote a program to generate a strobe pulse at the tip. But when there is a spike or noise anywhere in the signal, then I will get an unecessary or unwanted peak at this noise. Can anyone suggest how can I get right peak without using any filter to remove noise? I am doing it in VHDL
Help will be highly appreciated
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AXI read channel - signal rlast "missing"

January 17, 2014, 4:48 am
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Hi,

I try to get familiar with the AXI protocol. Therefore, I extended an example Design that comes along my EBV SoCrates Board (Lab1_solution). I use Quartus II Subscription Edition V13.1 under Debian Linux.

I created a custom component in QSYS that implements the AXI3 Interface. I added it to the existing system at the LWHPS2FPGA Interface at an Address 0x20000 which for the Linux that runs in the HPS is at address 0xff220000.
I have (from the example design) also a LED test component (Avalon MM Slave) that is accessible under 0xff200000 from the Linux on the HPS. Under Linux, in order to test the data transfer to the custom conponents, I use the tool devmem2. With that tool, I can switch on/off LEDs under the aforementioned LED component address.

Now, my AXI component just implements the Read address- and data-channels in order to read a counter value from that component with devmem2 from Linux.
I added signal tap to my custom component in oder to observe the data transaction.
In my understanding of the AXI data channel specification it is mandatory to switch the "rlast" signal from the slave once the last element of the data transfer is put on the bus. I implemented that signal in my custom component, but I'm not able to signal tap it because it is not in the post fitting netlist of my design (however, the wlast signal is there although I do not connect it in my test component.

The result of my devmem2 test from the Linux side is, that the call looks like a blocking call, that is never finished. In my opinion that is because the rlast signal is not applied and therefore the AXI transaction is not complete.

If you look at the attached signal tap screenshot then you see, that (after issuing the request from Linux) the correct address is called and the counter value is put onto the rdata bus. The only thing that is missing is the rlast signal that I do set in my vhdl component but I do not have a connection available in the QSYS generated component "SOC_System_hps_0_fpga_interfaces:fpga_interfaces. ..."

Additionally, I attach my custom component vhdl and tcl files in order for you to examine if I did something wrong there or if this maybe a bug in QSYS interconnect builder/Quartus Tool, that just not offers the rlast signal after synthesis/fitting.

I'm interested in your opinions on that.

Regards,
Maik
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Max V program download

January 17, 2014, 7:33 am
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I am new to the max v family and would like to use it in a safety application. It looks like the program is downloaded from internal EEprom on power up to set up the logic and the I/O. If this is right, does it do something like a verify checksum after the down load to verify the download. I have used the 7000 series in the past and I don't believe they have this download process, the program is set in the chip in EEprom. Am I understanding this correctly. Also it looks like support for the 7000 series is going away because I don't see support for the 7000 series in Quartus II v13.1
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Invalid logic levels at output of FPGA

January 17, 2014, 9:22 am
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Hi,

I've written a code for a state machine in an EP3C10F256 FPGA. I program the FPGA successfully but two of the FPGA outputs which correspond to two bits from a 16-bit register no not stand at any logic levels and they fluctuate somewhat like a mid-rail random sine wave with a low amplitude. I thought maybe the FPGA has a problem so I changed the pin assignment to a pin which was working moments before but got the same result.
The worst part is that when I'm trying to simulate the design Quartus freezes! (I'm not sure if this is the right place to also pose this problem but I'm not sure if it could also be a sign that there's something wrong with the code and it's implementation). The code is posted below: I'm looking at the outputs of the variable named "TimeCont".



module PixelTiming(
clk,
restart,
Decoder_Staggered,
Sample,
Shutter,
GlobRST,
GlobRST_Enable,
TimeCont,
error
);




input clk;
input restart;


output [0:7] Decoder_Staggered;
output Sample;
output Shutter;
output GlobRST;
output GlobRST_Enable;
output error;
output [0:15] TimeCont;


reg [7:0] Decoder_Staggered = 8'b00000000;
reg Sample;
reg Shutter;
reg GlobRST;
reg GlobRST_Enable;


reg [1:0] state = 2'b11;
reg [1:0] nextstate;
reg [15:0] timer = 0;
reg error = 1'b1;


wire [0:15] TimeCont = timer;








// ------------------------------------------------------------------------------------------------
// Time Parameters for 40MHz Clock => 25ns period


parameter T_init = 40 ;
parameter T_RowOn = 16'h0BB8 ;
parameter T_Pulse = 40 ;
parameter T_Column = 16'h0BB8 ;

parameter T_conversion = 16'h05DC ;


parameter S_Int = 2'b00;
parameter S_Conv = 2'b01;
parameter S_Reset = 2'b10;
parameter S_HARD_RESET = 2'b11;






always @(posedge clk) begin

if (restart == 0)
state <= S_HARD_RESET ;

else


state <= nextstate;



end


always @* begin



case(state)


S_HARD_RESET: begin

timer <=0;
nextstate = S_Int;

end



S_Int: begin


if (timer == T_Pulse) begin
GlobRST_Enable <= 1'b0;
GlobRST <= 1'b0;
Decoder_Staggered <= 8'h00;
nextstate = S_Conv;
timer <= 0;
end

else begin
timer <= timer + 1;
Sample <= 1'b0; //All pixels have rolling mode of operation
Shutter <= 1'b1;

GlobRST_Enable <= 1'b1;
GlobRST <= 1'b1;
Decoder_Staggered <= 8'hFF;
end

end



S_Conv: begin

if (timer == T_Column) begin
nextstate = S_Reset;
timer <= 0;
end
else
timer <= timer + 1;

end



S_Reset: begin

if (timer == T_Pulse) begin
nextstate = S_Conv;
GlobRST <= 1'b0;
Decoder_Staggered <= Decoder_Staggered + 1'b1;
timer <= 0;
end

else begin
timer <= timer + 1;
GlobRST <= 1'b1;
end

end

default: begin
nextstate = S_HARD_RESET;
end

endcase
end



endmodule
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Silly question: output hex value from DE1 to scope

January 17, 2014, 9:47 am
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Hello there,

Ok. I have a silly question about how to output hex value (16 bits) from Terasic DE1 to Tektronix O-scope through GPIO. I can see the counter in my Questasim, but now I want to see in hardware side.

Thanks,
Sean
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Stratix V timing constraints?

January 17, 2014, 9:50 am
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Hi,

I am trying to read data from a simple 8 channel 12 bit ADC using a Stratix V Gx dev kit.

Bitclock 480MHz
Frame Clock 80MHz

I try using source synchronous PLL megafunction for the bitclock and use the DDIO megafunction for reading the data.

But I can't meet timing.

I have checked rd07222013_432 solution already. But this patch doesn't fix my timing.

If i try the same PLL/DDIO on a stratix IV gx dev kit, I can meet timing constraints. But the Stratix V fails..

Is there something quirky with the Stratix V?
I'm guessing if simple DDIO doesn't work, ethernet/ddr3/pci express are a long shot..

Anybody else in the same boat as me?

I have submitted a service request.. Lets see.

Thanks
ZubairLK
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Beginner question about making a beep sound

January 17, 2014, 10:49 am
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I am so sorry to ask such a simple question, which i have been thinking for whole night already.
Here are the codes

module music(clk, speaker);
input clk;
output speaker;

reg [15:0] counter;
always @(posedge clk) counter <= counter+1;

assign speaker = counter[15];
endmodule

My question is :
1. Anyone can explain the logic to me. I very a beginner.
2. " always@(posedge clk) counter <= counter+1;" means it has positive clock only when counter is smaller than counter +1, but what is counter physically in this case??
3. Assign speaker to one of the value of counter is understandable, however, why then the speak will make a sound of frequency 381Hz if the input clock is set to be 25MHz, i know it's from 25MHz/65536= 381Hz, but i just dont understand why. how come? what is happening here?

Anyone can explain this? i will appreciate that. Thank you so much:oops:
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#include in kernel

January 17, 2014, 11:53 am
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Hi folks,

I need some tiny bit of help here. In my kernel.cl, I have an #include preprocessor directive:

#include Headers/HashSetKernelFind.h

I can't seem to get the -I option of aoc on the command line to work, which I need because I have to run aoc in another directory on the same level as the "Headers" one. So I do this:

aoc -I ../ kernel.cl

But I just get:

aoc: Running OpenCL parser....
c:/path/to/project/GraphPurger/kernel.cl:1:10: fatal error: 'Headers/HashSetKernelFind.h' file not found
#include "Headers/HashSetKernelFind.h"
^
1 error generated.
Error: OpenCL parser FAILED.
Refer to kernel.log for details.

What am I doing wrong? The same works with AMD APP SDK and Intel OpenCL SDK.
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PLL location assignment

January 17, 2014, 12:02 pm
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Hi,
When i use Altpll to design a PLL, how do i know where the designed PLL will be? Or, how do i assign a PLL to be used at a specific location so that i can assign a input pin for it?
Thanks

Yaoting

I am using Cyclone IV GX, EP4CGX150DF27C7
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system.h missing /dev/dma_0, but DMA device is in the top.socpinfo file

January 17, 2014, 2:19 pm
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I have a working FPGA design with PCIe + DMA + JTAG_UART + NIOS II + Internal Memory.

I have been asked to move to a HAL design for the the C code running on NIOS II.

I have got to the point of the Eclipse Hello world free_standing application with the alt_main entry point.

/* Obtain a handle for the device */
if ((rx = alt_dma_rxchan_open ("/dev/dma_0")) == NULL)

fails to open the rx channel ... investigating , the system.h generated is missing the anything that has *DMA* in it.
the top.socpinfo does contain the DMA device and the JTAG_UART device

<instanceCount>1</instanceCount>
<name>altera_avalon_dma</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>DMA Controller</displayName>
<version>13.0.1.99.2</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>altera_avalon_jtag_uart</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>JTAG UART</displayName>
<version>13.0.1.99.2</version>



Any ideas on why the top.socpinfo device info. for the DMA controller is not getting into the system.h file ?

I assume the open of the /dev/dma_0 is failing if the system.h is missing any DMA device ... however I will run debug on the code as I have seen forum entries
indicating the device list search for the /dev/dma_0 was failing ....

Any advice appreciated. Bob.
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DDR3 SDRAM Unimemphy issue with qsys design

January 17, 2014, 9:29 pm
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Hi there,

I am beginner with DDR3 and try to integrate DDR3 SDRAM(MT41J128M16) with NIOS.My qsys design is having NIOS,DDR3 SDRAM Controller,JTAG UART and interconnect bridges.
The issue is that when i generate the qsys design its get generated successfully but having warning with
"Warning: System.ddr3_bot: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors."
should i ignore this warning or is there any parameter that i have missed to configure properly.



waiting for your reply. :(

regards,
Hitesh Zanzmera
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LVDS mega function implementation in Cyclone III

January 17, 2014, 11:50 pm
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iam trying to implement LVDS TX by connecting inputs from VIP clocked video output . requirement is to generate 3 LVDS channels for R,G , B and a differential clock signal . How to implement differential clock output from LVDS TX?
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FPGA Implementation for wireless transmission of output data from ASUS Xtion Pro.

January 18, 2014, 2:53 am
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i would like to transmit the output of ASUS Xtion Pro via wi-fi and i want to use FPGA to implement this. is it feasible?
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How to download code to ARM processor from the command line

January 18, 2014, 6:49 am
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Hi,
As far as I understand the flow:
1. Create the qsys system
2. Create the bsp.
3. Import the bsp into DS-5 and download to the ARM on the cyclone 5.

The problem is that only the subscription edition of DS-5 has the option to download code to the ARM core and I am trying to use the community edition (the sockit is for hobby use so I don't want to fork out a lot of money for software).

So how can I get the code running on the board from the USB Blaster II. There must be a command line program to do something like this right or are we all required to get the subscription edition of DS-5 to use these devices?

Regards,
Scott
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DE0 Nano with SDRAM and EPCS not loading firmware

January 18, 2014, 11:48 am
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I have configured the DE0 Nano with a SDRAM, EPCS, and ALTPLL combo that phase shift the SDRAM clock -3ns as required. When I use the flash programmer it completes flashing successfully, restarting the DE0 shows that the VHDL logic is working, but the firmware is not running. Running the system as Nios II Hardware from the nios II ide works fine.

I suspected this may be PLL not generating clocks correctly so I instead used the University IP DE clocks , the result is still the same. Assuming that I did not set this system up correctly I ran the the DE0_Nano_QSYS_DEMO downloaded from the terasic website (DE0_Nano_V.1.2.0_CDROM) which contains a project that uses the EPCS,SDRAM, and ALTPLL. The same thing happens, it flashes successfully but the firmware doesn't seem to be loading while the VHDL logic is running fine.

I tried this on both Quartus v11.0 and v13. I have also added the nios2-flash-override.txt patch file for EPCS. I've also tried this on two De0 nano boards purchased from terasic (2013) and digikey (2014) thinking the board might be bad but the same result.

Everything works fine if I switch from SDRAM to on-chip memory, I can flash and the system runs both hardware and firmware, but I would like to use the SDRAM as the on-chip memory is too small.

I'm thinking I need to create a synopsis design constraints file, am I required to create a ".sdc" file when ever I use a PLL? is there somewhere that I can download a recent sample project that has the SDRAM, EPCS and PLL working?
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Program Counter using VHDL for Altera DE2 Board.

January 18, 2014, 2:46 pm
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Hi guys noob here, first post. I need to design a program counter to satisfy the following schematic.


pc.jpg


and here is my code so far. Now I'm pretty sure this is wrong. But I don't even know how to test this yet using QuartusII, hoping my TA will explain it this Monday. Would someone with more experience take a look and help me figure this out, in particular I am sure I implemented the inc (increment) condition wrong, that is, if inc is high then I should start the count from the output.


Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY pc IS
        PORT(
                clr : IN STD_LOGIC;
                clk : IN STD_LOGIC;
                ld  : IN STD_LOGIC;
                inc : IN STD_LOGIC;
                d  : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                q  : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END pc;
ARCHITECTURE description OF pc IS
-- you fill in what goes here!!!
        SIGNAL Count:STD_LOGIC_VECTOR (31 DOWNTO 0) ;
        BEGIN
                PROCESS (clk,clr,ld,inc)
                BEGIN
                        IF clr='0' THEN
                                Count<="00000000000000000000000000000000";
                        ELSIF inc='1' THEN
                                Count<=q;
                        ELSIF (clk'EVENT AND clk = '1') THEN
                                IF ld='1' THEN
                                        Count<=Count+4;
                                ELSE
                                        Count<=Count;
                                END IF;
                        END IF;
                END PROCESS;
                q<=Count;
END description;

any help would be greatly appreciated, thanks in advanced.
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How to setup the Quartus 13,1 in Ubuntu 12.4.1?

January 18, 2014, 3:04 pm
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I am new about the Quartus in Linux (also new in Linux). I just install Quartus 13.1 in my Ubuntu. Then I can only start Quartus in the folder I installed. How should I do setup that I can start Quartus through command "quartus" in any directory?

Thanks very much.
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CoreSight ETR (Embedded Trace Router) readable from Linux

January 18, 2014, 3:01 pm
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Hello, I have two questions regarding the ARM CPU (HPS) in the Cyclone V boards. 1.) Do only the Cyclone V S[x] products have the ARM CPU on board? (Table "The Family Comes in Six Targeted Variants" at http://www.altera.com/devices/fpga/c.../cyv-index.jsp seems to suggest so) 2.) Is it possible to configure the CoreSight ETM (embedded trace macrocell) in ETR (embedded trace router) mode to store instruction/data traces to main system memory and retreive the recorded traces from linux? thank's for your answers/pointers --m
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crash report

January 19, 2014, 3:00 am
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Hello, my Quartus is crashed, and I have web edition so can't find any other option to report it:

Code:

Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/database/netlist.cpp, Line: 5102
n && n->Owner() == this
Stack Trace:
    0x42e30: vrfx_altera_assert + 0x20
    0x97136: Netlist::RegisterPotentiallyFanoutFreeNet + 0x86
    0xea349: VeriNonConstVal::NetAssignFrom + 0x139
  0x16240e: VeriAlwaysConstruct::Elaborate + 0x24e
    0xd0064: VeriModule::Elaborate + 0x74
    0xd456f: VeriModule::Elaborate + 0x56f
    0x5c342: VRFX_VERIFIC_VERILOG_ELABORATOR::elaborate + 0x482
    0x5747f: VRFX_ELABORATOR::elaborate + 0xdf
    0xad8d4: SGN_FN_LIB::elaborate + 0x124
    0xb03aa: SGN_FN_LIB::start_vrf_flow + 0xa
    0xb158d: SGN_FN_LIB::start + 0x55d
    0x8301f: SGN_EXTRACTOR::single_module_extraction + 0x17f
    0x90482: SGN_EXTRACTOR::recursive_extraction + 0x192
    0x8e00e: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist + 0x2de
    0x904c3: SGN_EXTRACTOR::recursive_extraction + 0x1d3
    0x8e00e: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist + 0x2de
    0x904c3: SGN_EXTRACTOR::recursive_extraction + 0x1d3
    0x93b81: SGN_EXTRACTOR::extract + 0x1b1
    0x12bb2: sgn_qic_full + 0x142
    0x464d: qsyn_execute_sgn + 0x11d
    0x1c924: QSYN_FRAMEWORK::execute_core + 0x104
    0x1f23a: QSYN_FRAMEWORK::execute + 0x26a
    0x111b7: qexe_get_tcl_sub_option + 0x1b87
    0x13ad6: qexe_process_cmdline_arguments + 0x526
    0x13bd4: qexe_standard_main + 0x84
    0x19dd6: qsyn_main + 0xa6
    0x4e21: msg_main_thread + 0x11
    0x1c98: _thr_final_wrapper + 0x8
    0x5515: msg_thread_wrapper + 0x85
    0x3921: mem_thread_wrapper + 0x31
    0x60f1: msg_exe_main + 0x81
    0x1ba1c: _main + 0x1c
    0x24cd7: __ftol2 + 0x1e1
    0x4ed5b: BaseThreadInitThunk + 0x11
    0x637ea: RtlInitializeExceptionChain + 0xee
    0x637bd: RtlInitializeExceptionChain + 0xc1

End-trace

Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 SJ Web Edition
Service Pack Installed:  1
And this is the code caused it, look around 'ribbon' object:

Code:


module VGA_HighEnd ( clk, rst,
                                iX_video, iY_video,
                                oR_video, oG_video, oB_video,
                                tumblers, endFrame, dbg_val    );

parameter RES_X_H= 1240;
parameter RES_Y_H= 1024;
parameter XY_STEP_H= 7;
parameter RES_X_L= 640;
parameter RES_Y_L= 480;
parameter XY_STEP_L= 8;

input clk;
input rst;

input signed [11:0] iX_video;
input signed [11:0] iY_video;
output reg [7:0] oR_video;
output reg [7:0] oG_video;
output reg [7:0] oB_video;
input    [9:0]            tumblers;
input endFrame;
output wire [63:0] dbg_val;

wire [31:0] V_out2;

wire high_res= 1;

reg [15:0] count;


wire signed [11:0] x;
wire signed [11:0] y;
assign x= (iX_video- (high_res ? RES_X_H/2 :RES_X_L/2 ));
assign y= (iY_video- (high_res ? RES_Y_H/2 :RES_Y_L/2 ));

//reg [31:0]ribbon;//    NO CRASH

always@(posedge clk or posedge rst)
begin
    if ( rst )
    begin
        count= 0;
    end
    else
    begin
        if ( endFrame )
        begin
            count<= count +1;
            ribbon[15:0] <=count;
        end
        //    Y'UV ->RGB
        oR_video= {7{ribbon[iX_video]}};
        oG_video= count;
        oB_video= -1;
    end
end
endmodule

reg [31:0]ribbon;//    CRASH            !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
//reg [15:0]ribbon;//    NO CRASH
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